SCES928B April 2021 – January 2024 SN74AXC2T45-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in Section 5.5. The worst case resistance is calculated with the maximum input voltage, given in Section 5.1, and the maximum input leakage current, given in the Section 5.5, using Ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Section 5.3 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.