SCES883C December   2018  – September 2020 SN74AXCH1T45

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 0.7 V
    7. 6.7  Switching Characteristics, VCCA = 0.8 V
    8. 6.8  Switching Characteristics, VCCA = 0.9 V
    9. 6.9  Switching Characteristics, VCCA = 1.2 V
    10. 6.10 Switching Characteristics, VCCA = 1.5 V
    11. 6.11 Switching Characteristics, VCCA = 1.8 V
    12. 6.12 Switching Characteristics, VCCA = 2.5 V
    13. 6.13 Switching Characteristics, VCCA = 3.3 V
    14. 6.14 Operating Characteristics: TA = 25°C
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Standard CMOS Inputs
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation
      5. 8.3.5 Over-Voltage Tolerant Inputs
      6. 8.3.6 Negative Clamping Diodes
      7. 8.3.7 Fully Configurable Dual-Rail Design
      8. 8.3.8 Supports High-Speed Translation
      9. 8.3.9 Bus-Hold Data Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Enable Times
    2. 9.2 Typical Applications
      1. 9.2.1 Interrupt Request Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Universal Asynchronous Receiver-Transmitter (UART) Interface Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.9 Bus-Hold Data Inputs

Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low state. After data has been sent through a channel, the latch then maintains the previous state on the input if the line is left floating. It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may cause undefined inputs to occur which leads to excessive current consumption.

Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs application report explains the problems associated with leaving CMOS inputs floating.

These latches remain active at all times, independent of all control signals such as direction control or output enable.

The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.

GUID-896320F2-F124-439C-A22D-A4A9BD2162E9-low.gifFigure 8-2 Simplified Schematic for Device With Bus-Hold Data Inputs