SLASFD9 April   2025 TAC5301-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements: I2C Interface
    8. 5.8  Switching Characteristics: I2C Interface
    9. 5.9  Timing Requirements: TDM, I2S or LJ Interface
    10. 5.10 Switching Characteristics: TDM, I2S or LJ Interface
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Charactaristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Input Channel Configuration
      4. 6.3.4 Output Channel Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2  Programmable Channel Gain Calibration
          3. 6.3.7.1.3  Programmable Channel Phase Calibration
          4. 6.3.7.1.4  Programmable Digital High-Pass Filter
          5. 6.3.7.1.5  Programmable Digital Biquad Filters
          6. 6.3.7.1.6  Programmable Channel Summer and Digital Mixer
          7. 6.3.7.1.7  Configurable Digital Decimation Filters
            1. 6.3.7.1.7.1 Linear-phase filters
              1. 6.3.7.1.7.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.7.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.7.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.7.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.7.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.7.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.7.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.1.7.2 Low-latency Filters
              1. 6.3.7.1.7.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.7.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.7.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.7.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.7.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.7.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.7.3.5 Sampling Rate: 192kHz or 176.4kHz
          8. 6.3.7.1.8  Automatic Gain Controller (AGC)
          9. 6.3.7.1.9  Voice Activity Detection (VAD)
          10. 6.3.7.1.10 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 General I2C Operation
        2. 6.5.1.2 I2C Single-Byte and Multiple-Byte Transfers
          1. 6.5.1.2.1 I2C Single-Byte Write
          2. 6.5.1.2.2 I2C Multiple-Byte Write
          3. 6.5.1.2.3 I2C Single-Byte Read
          4. 6.5.1.2.4 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5301-Q1_B0_P0 Registers
      2. 7.1.2 TAC5301-Q1_B0_P1 Registers
      3. 7.1.3 TAC5301-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Example
      2. 8.4.2 Layout Guidelines
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode, PLL on, channel gain = 0dB, linear phase interpolation filters, 1200Ω/600Ω line-out load in differential/single-ended configuration or 32Ω/16Ω receiver/headphone load as applicable, MICBIAS programmed to VREF, and other default configurations; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted bandwidth, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DAC Performance for Line Output/Head Phone Playback
Full Scale Output Voltage Differential output between OUTxP and OUTxM, AVDD = 3.3V 2 VRMS
Single-ended output, AVDD = 3.3V 1
Pseudo-differential output between OUTxP and OUTxM, AVDD = 3.3V 1
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential output, 0dBFS signal, AVDD=3.3V 110 dB
Single-ended output, 0dBFS signal, AVDD=3.3V 107
Pseudo-differential output, 0dBFS signal, AVDD=3.3V 108
Differential output, 0dBFS signal, AVDD=3.3V, Power Tune Mode(3) 105
Single-ended output, 0dBFS signal, AVDD=3.3V, Power Tune Mode(3) 103
Pseudo-differential output, 0dBFS signal, AVDD=3.3V, Power Tune Mode(3) 106
SNR Signal-to-noise ratio, A-weighted(1)(2) Differential output, Receiver load, 0dBFS signal, AVDD=3.3V 109 dB
Single-ended output, Headphone load, 0dBFS signal, AVDD=3.3V 107
Pseudo-differential output, Receiver load, 0dBFS signal, AVDD=3.3V 108
DR Dynamic range, A-weighted(2) Differential output, -60dBFS signal, AVDD=3.3V 110 dB
Single-ended output, -60dBFS signal, AVDD=3.3V 107
Pseudo-differential output, -60dBFS signal, AVDD=3.3V 108
Differential output, -60dBFS signal, AVDD=3.3V, Power Tune Mode(3) 105
Single-ended output, -60dBFS signal, AVDD=3.3V, Power Tune Mode(3) 103
Pseudo-differential output, -60dBFS signal, AVDD=3.3V, Power Tune Mode(3) 107
DR Dynamic range, A-weighted(2) Differential-output, Receiver load, -60dBFS signal, AVDD=3.3V 109 dB
Single-ended output, Headphone load, -60dBFS signal, AVDD=3.3V 107
Pseudo-differential output, Receiver load, -60dBFS signal, AVDD=3.3V 108
THD+N Total harmonic distortion(2) Differential output, –1dBFS signal, AVDD= 3.3V –101 dB
Headphone load range Single-ended 4 16 600 Ω
Line-out load range Single-ended 600 Ω
Headphone/Line-out Cap load Single-ended 0 2 nF
DAC Channel OTHER PARAMETERS
Output Offset 0 Input, Differential line-output ±0.5 mV
Output Common Mode Common Mode Level for OUTxP and OUTxM AVDD = 3.3V (Register Configurable) 1.65 V
Common Mode Error DC Error in Common Mode Voltage ±20 mV
Output Signal Bandwidth Up to 192KSPS FS Rate 0.46 FS
>192KSPS 90 kHz
Input data sample rate Programmable 4 768 kHz
Input data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3dB point (default setting)		 1 Hz
Gain Error Differential output, –6dBFS Input signal ±0.1 dB
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential output, 0dB channel gain 110 dB
Mute Attenuation –130 dB
Pout Output Power Delivery Single-ended/Pseudo-differential headphone RL=16Ω, THD+N<0.1% 62.5 mW
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with no generator input signal and input shorted to ground, measured with an A-weighted filter over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20kHz low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter can result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) PWR_TUNE_CFG0 = 0xD4, PWR_TUNE_CFG1 = 0x96 and PLL_DIS = 1'b1 for Power Tune Mode