SLASEM6E october   2017  – july 2023 TAS2770

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 TDM Port Timing Requirements
    8. 6.8 PDM Port Timing Requirements
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Mode and Address Selection
      2. 8.3.2 General I2C Operation
      3. 8.3.3 Single-Byte and Multiple-Byte Transfers
      4. 8.3.4 Single-Byte Write
      5. 8.3.5 Multiple-Byte Write and Incremental Multiple-Byte Write
      6. 8.3.6 Single-Byte Read
      7. 8.3.7 Multiple-Byte Read
      8. 8.3.8 Register Organization
    4. 8.4 Device Functional Modes
      1. 8.4.1  PDM Input
      2. 8.4.2  TDM Port
      3. 8.4.3  Playback Signal Path
        1. 8.4.3.1 High Pass Filter
        2. 8.4.3.2 Digital Volume Control and Amplifier Output Level
        3. 8.4.3.3 Audio Playback Selection
        4. 8.4.3.4 Battery Tracking Limiter with Brown Out Prevention
        5. 8.4.3.5 Inter Chip Limiter Alignment
          1. 8.4.3.5.1 TDM Mode
        6. 8.4.3.6 Class-D Settings
      4. 8.4.4  SAR ADC
      5. 8.4.5  IV Sense
      6. 8.4.6  Clocks and PLL
      7. 8.4.7  Operational Modes
        1. 8.4.7.1 Hardware Shutdown
        2. 8.4.7.2 Software Shutdown
        3. 8.4.7.3 Mute
        4. 8.4.7.4 Active
        5. 8.4.7.5 Mode Control and Software Reset
      8. 8.4.8  Faults and Status
      9. 8.4.9  Power Sequencing Requirements
      10. 8.4.10 Digital Input Pull Downs
    5. 8.5 Register Maps
      1. 8.5.1 Register Summary Table Book=0x00 Page=0x00
      2. 8.5.2 Register Maps
        1. 8.5.2.1  PAGE (book=0x00 page=0x00 address=0x00) [reset=0h]
        2. 8.5.2.2  SW_RESET (book=0x00 page=0x00 address=0x01) [reset=0h]
        3. 8.5.2.3  PWR_CTL (book=0x00 page=0x00 address=0x02) [reset=Eh]
        4. 8.5.2.4  PB_CFG0 (book=0x00 page=0x00 address=0x03) [reset=10h]
        5. 8.5.2.5  PB_CFG1 (book=0x00 page=0x00 address=0x04) [reset=1h]
        6. 8.5.2.6  PB_CFG2 (book=0x00 page=0x00 address=0x05) [reset=0h]
        7. 8.5.2.7  PB_CFG3 (book=0x00 page=0x00 address=0x06) [reset=0h]
        8. 8.5.2.8  MISC_CFG (book=0x00 page=0x00 address=0x07) [reset=6h]
        9. 8.5.2.9  PDM_CFG0 (book=0x00 page=0x00 address=0x08) [reset=0h]
        10. 8.5.2.10 PDM_CFG1 (book=0x00 page=0x00 address=0x09) [reset=8h]
        11. 8.5.2.11 TDM_CFG0 (book=0x00 page=0x00 address=0x0A) [reset=7h]
        12. 8.5.2.12 TDM_CFG1 (book=0x00 page=0x00 address=0x0B) [reset=2h]
        13. 8.5.2.13 TDM_CFG2 (book=0x00 page=0x00 address=0x0C) [reset=Ah]
        14. 8.5.2.14 TDM_CFG3 (book=0x00 page=0x00 address=0x0D) [reset=10h]
        15. 8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h]
        16. 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h]
        17. 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h]
        18. 8.5.2.18 TDM_CFG7 (book=0x00 page=0x00 address=0x11) [reset=4h]
        19. 8.5.2.19 TDM_CFG8 (book=0x00 page=0x00 address=0x12) [reset=6h]
        20. 8.5.2.20 TDM_CFG9 (book=0x00 page=0x00 address=0x13) [reset=7h]
        21. 8.5.2.21 TDM_CFG10 (book=0x00 page=0x00 address=0x14) [reset=8h]
        22. 8.5.2.22 LIM_CFG0 (book=0x00 page=0x00 address=0x15) [reset=14h]
        23. 8.5.2.23 LIM_CFG1 (book=0x00 page=0x00 address=0x16) [reset=76h]
        24. 8.5.2.24 LIM_CFG2 (book=0x00 page=0x00 address=0x17) [reset=10h]
        25. 8.5.2.25 LIM_CFG3 (book=0x00 page=0x00 address=0x18) [reset=6Eh]
        26. 8.5.2.26 LIM_CFG4 (book=0x00 page=0x00 address=0x19) [reset=1Eh]
        27. 8.5.2.27 LIM_CFG5 (book=0x00 page=0x00 address=0x1A) [reset=58h]
        28. 8.5.2.28 BOP_CFG0 (book=0x00 page=0x00 address=0x1B) [reset=1h]
        29. 8.5.2.29 BOP_CFG1 (book=0x00 page=0x00 address=0x1C) [reset=14h]
        30. 8.5.2.30 BOP_CFG2 (book=0x00 page=0x00 address=0x1D) [reset=4Eh]
        31. 8.5.2.31 ICLA_CFG0 (book=0x00 page=0x00 address=0x1E) [reset=0h]
        32. 8.5.2.32 ICLA_CFG1 (book=0x00 page=0x00 address=0x1F) [reset=0h]
        33. 8.5.2.33 INT_MASK0 (book=0x00 page=0x00 address=0x20) [reset=FCh]
        34. 8.5.2.34 INT_MASK1 (book=0x00 page=0x00 address=0x21) [reset=B1h]
        35. 8.5.2.35 INT_LIVE0 (book=0x00 page=0x00 address=0x22) [reset=0h]
        36. 8.5.2.36 INT_LIVE1 (book=0x00 page=0x00 address=0x23) [reset=0h]
        37. 8.5.2.37 INT_LTCH0 (book=0x00 page=0x00 address=0x24) [reset=0h]
        38. 8.5.2.38 INT_LTCH1 (book=0x00 page=0x00 address=0x25) [reset=0h]
        39. 8.5.2.39 INT_LTCH2 (book=0x00 page=0x00 address=0x26) [reset=0h]
        40. 8.5.2.40 VBAT_MSB (book=0x00 page=0x00 address=0x27) [reset=0h]
        41. 8.5.2.41 VBAT_LSB (book=0x00 page=0x00 address=0x28) [reset=0h]
        42. 8.5.2.42 TEMP_MSB (book=0x00 page=0x00 address=0x29) [reset=0h]
        43. 8.5.2.43 TEMP_LSB (book=0x00 page=0x00 address=0x2A) [reset=0h]
        44. 8.5.2.44 INT_CFG (book=0x00 page=0x00 address=0x30) [reset=5h]
        45. 8.5.2.45 DIN_PD (book=0x00 page=0x00 address=0x31) [reset=0h]
        46. 8.5.2.46 MISC_IRQ (book=0x00 page=0x00 address=0x32) [reset=81h]
        47. 8.5.2.47 CLOCK_CFG (book=0x00 page=0x00 address=0x3C) [reset=Dh]
        48. 8.5.2.48 TDM_DET (book=0x00 page=0x00 address=0x77) [reset=7Fh]
        49. 8.5.2.49 REV_ID (book=0x00 page=0x00 address=0x7D) [reset=20h]
        50. 8.5.2.50 I2C_CKSUM (book=0x00 page=0x00 address=0x7E) [reset=0h]
        51. 8.5.2.51 BOOK (book=0x00 page=0x00 address=0x7F) [reset=0h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Overview
        2. 9.2.2.2 Select Input Capacitance
        3. 9.2.2.3 Select Decoupling Capacitors
        4. 9.2.2.4 Select Bootstrap Capacitors
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Initial Device Configuration - Auto Rate
      2. 9.3.2 Initial Device Configuration - 48 kHz
      3. 9.3.3 Initial Device Configuration - 44.1 kHz
      4. 9.3.4 Sample Rate Change - 48 kHz to 44.1kHz
      5. 9.3.5 Sample Rate Change - 44.1 kHz to 48 kHz
      6. 9.3.6 Device Mute
      7. 9.3.7 Device Un-Mute
      8. 9.3.8 Device Sleep
      9. 9.3.9 Device Wake
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TA = 25 °C, VBAT = 12.6 V, AVDD = IOVDD = 1.8 V, RL = 4 Ω + 33 µH, fin = 1 kHz, SSM, fs = 48 kHz, Gain = 21 dBV, SDZ = 1, Measured filter free using Section 7 (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DIGITAL INPUT and OUTPUT
VIHHigh-level digital input logic voltage thresholdAll digital pins except SDA and SCL; IOVDD = 1.8 V.0.65 × IOVDDV
VILLow-level digital input logic voltage thresholdAll digital pins except SDA and SCL; IOVDD = 1.8 V.0.35 × IOVDDV
VIH(I2C)High-level digital input logic voltage thresholdSDA and SCL; IOVDD = 1.8 V.0.7 x IOVDDV
VIL(I2C)Low-level digital input logic voltage thresholdSDA and SCL; IOVDD = 1.8 V.0.3 x IOVDDV
VOHHigh-level digital output voltageAll digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOH = 2 mA.IOVDD – 0.45 VV
VOLLow-level digital output voltageAll digital pins except SDA, SCL and IRQZ; IOVDD = 1.8 V; IOL = –2 mA.0.45V
VOL(I2C)Low-level digital output voltageSDA and SCL; IOVDD = 1.8 V; IOL(I2C) = –2 mA.0.2 x IOVDDV
VOL(IRQZ)Low-level digital output voltage for IRQZ open drain OutputIRQZ; IOVDD = 1.8 V; IOL(IRQZ) = –2 mA.0.45V
IIHInput logic-high leakage for digital inputsAll digital pins; Input = IOVDD.–50.15µA
IILInput logic-low leakage for digital inputsAll digital pins; Input = GND.–50.15µA
CINInput capacitance for digital inputsAll digital pins5pF
RPDPull down resistance for digital input/IO pins when asserted onSDOUT, SDIN, FSYNC, SBCLK, PDMD, PDMCK18kΩ
TDM SERIAL AUDIO PORT
PCM Sample Rates & FSYNC Input FrequencySingle Speed, I2S/TDM Operation48kHz
Double Speed, I2S/TDM Operation96
Quadruple Speed, I2S/TDM Operation192
SBCLK Input FrequencyI2S/TDM Operation2.5427.1MHz
SBCLK Maximum Input JitterRMS Jitter below 40 kHz that can be tolerated without performance degradation1ns
RMS Jitter above 40 kHz that can be tolerated without performance degradation10
SBCLK Cycles per FSYNC in I2S and TDM ModesValues: 64, 96, 128, 192, 256, 384 and 51264512Cycles
PDM AUDIO PORT
PDM clock input frequencySingle Rate PDM3.072MHz
Double Rate PDM6.144
PDM sensor clock rate to PCM sample rate oversampling ratiosSingle Speed PCM. Values: 64X and 128X.64128
Double Speed PCM. Values: 32X and 64X.3264
Quadruple Speed PCM. Values: 16X and 32X.1632
PROTECTION CIRCUITRY
Thermal shutdown temperature140°C
Thermal shutdown retry1.5s
VBAT undervoltage lockout threshold (UVLO)UVLO is asserted4V
VBAT overvoltage lockout threshold (OVLO)OVLO is asserted18V
AMPLIFIER PERFORMANCE
POUTMaximum Continuous Output Power 0.1% THD+NRL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V3.7W
RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 8.4 V6.6
RL = 8 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V8.5
RL = 4 Ω + 33 µH, THD+N = 0.1 %, fin = 1 kHz, VBAT = 12.6 V14.2
Maximum Continuous Output Power 1% THD+NRL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V4
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 8.4 V7.1
RL = 8 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V9.1
RL = 4 Ω + 33 µH, THD+N = 1 %, fin = 1 kHz, VBAT = 12.6 V15.4
System efficiency at POUT = 1 WRL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V89 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 8.4 V84 %
RL = 8 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V87.5 %
RL = 4 Ω + 33 µH, fin = 1 kHz, VBAT = 12.6 V82.7 %
System efficiency at 0.1% THD+N power levelRL = 8 Ω + 33 µH, POUT = 3. 7W, fin = 1 kHz, VBAT = 8.4 V92 %
RL = 4 Ω + 33 µH, POUT = 6.6 W, fin = 1 kHz, VBAT = 8.4 V87 %
RL = 8 Ω + 33 µH, POUT = 8.5 W, fin = 1 kHz, VBAT = 12.6 V92 %
RL = 4 Ω + 33 µH, POUT = 14.2 W, fin = 1 kHz, VBAT = 12.6 V86 %
THD+NTotal harmonic distortion + noisePOUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 8.4 V0.01 %
POUT = 1 W, RL = 8 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V0.01 %
POUT = 1 W, RL = 4 Ω + 33 µH, fin = 20 Hz - 20 kHz, VBAT = 12.6 V0.01 %
VNIdle channel noiseA-Weighted, 20 Hz - 20 kHz, DAC Modulator Running31µV
VBAT = 8.4 V32µV
VBAT = 12.6 V36µV
FPWMClass-D PWM switching frequencyAverage frequency in Spread Spectrum Mode, CLASSD_SYNC=0384kHz
Fixed Frequency Mode, CLASSD_SYNC=0345.6384422.4
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 44.1, 88.2, 174.6 kHz44.1·8
Fixed Frequency Mode, CLASSD_SYNC=1, fs = 48, 96, 192 kHz48·8
VOSOutput offset voltage-11mV
DNRDynamic rangeA-Weighted, -60 dBFS Method108dB
SNRSignal to noise ratioA-Weighted, Referenced to 1 % THD+N Output Level108dB
KCPClick and pop performanceInto and out of Mute, Shutdown, Power Up, Power Down and audio clocks starting and stopping. A-weighted5mV
Programmable output level range12.521dBV
Programmable output level step size0.5dB
AVERRORAmplifier gain errorPOUT=1W±0.1dB
ARIPPLEFrequency response passband ripple20 Hz - 20 kHz±0.1dB
Mute attenuationDevice in Shutdown or Muted in Normal Operation110dB
Output short circuit limitVBAT = 12.6 V, Output to Output, Output to GND or Output to VBAT Short6A
RDS(ON)FETPower stage on-resistance (high-side + low-side + sense resistor)TA = 25 °C510mΩ
VBAT power-supply rejection ratioVBAT = 12.6 V + 200 mVpp, fripple = 217 Hz105dB
VBAT = 12.6 V + 200 mVpp, fripple = 20 kHz86
AVDD power-supply rejection ratioAVDD = 1.8 V + 200 mVpp, fripple = 217 Hz95dB
AVDD = 1.8 V + 200 mVpp, fripple = 20 kHz88
Turn on time from release of SW shutdownNo Volume Ramping1.2ms
Volume Ramping5.3
Turn off time from assertion of SW shutdown to amp Hi-ZNo Volume Ramping0.3ms
Volume Ramping4.7
PCM PLAYBACK CHARACTERISTICS
Playback latency from latched input sample to speaker terminalsSingle Speed, I2S/TDM3.5samples
Double Speed, I2S/TDM3.5
Quadruple Speed, I2S/TDM3.5
Playback –0.1 dB bandwidthSingle Speed, I2S/TDM23.06kHz
Double Speed, I2S/TDM21.79
Quadruple Speed, I2S/TDM21.69
Playback –3 dB bandwidthSingle Speed, I2S/TDM24kHz
Double Speed, I2S/TDM23
Quadruple Speed, I2S/TDM27.26
PDM PLAYBACK CHARACTERISTICS
Playback latency from latched data bit to speaker terminalsSingle Rate PDM, PDMD input7.07µs
Double Rate PDM, PDMD input5.02
Playback –0.1 dB bandwidthSingle Rate PDM, PDMD input41.5kHz
Double Rate PDM, PDMD input88
Playback –3 dB bandwidthSingle Rate PDM, PDMD input77.5kHz
Double Rate PDM, PDMD input143
SPEAKER CURRENT SENSE
DNRDynamic rangeUn-Weighted, Relative to 0 dBFS69dB
THD+NTotal harmonic distortion + noiseRL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W–60dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W–60
Full-scale input current3.75A
Current-sense accuracyRL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W)±1 %
Current-sense gain error over temperature–20°C to 70°C, POUT = 1 W±0.75%
Current-sense gain error over output power50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone±0.75%
Current-sense frequency responseMax deviation above and below passband gain±0.2dB
SPEAKER VOLTAGE SENSE
DNRDynamic rangeUn-Weighted, Relative 0 dBFS69dB
THD+NTotal harmonic distortion + noiseRL = 8 Ω + 33 µH, fin = 1 kHz, POUT = 5 W–60dB
RL = 4 Ω + 33 µH, fin = 1 kHz, POUT = 7.5 W–60
Full-scale input voltage14VPK
Voltage-sense accuracyRL = 8 Ω + 33 µH, IOUT = 354 mARMS (POUT = 1 W)±1%
Voltage-sense gain error over temperature–20°C to 70°C, POUT = 1 W±0.75%
Voltage-sense gain error over output power50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone±0.75%
Voltage-sense frequency responseMax deviation above and below passband gain±0.2dB
SPEAKER VOLTAGE/CURRENT SENSE RATIO
Gain ratio error over output power50 mW to 0.1 % THD+N level, fin = 1 kHz, 4 Ω, using a 40Hz-34dB pilot tone±0.75%
Gain ratio error over temperature–20°C to 70°C±0.5%
TYPICAL CURRENT CONSUMPTION
Current consumption in hardware shutdownSDZ = 0, VBAT0.1µA
SDZ = 0, AVDD1
SDZ = 0, IOVDD0.1
Current consumption in software shutdownAll Clocks Stopped, VBAT10µA
All Clocks Stopped, AVDD10
All Clocks Stopped, IOVDD1
Current consumption during active operation with IV sense disabledfs = 48 kHz, VBAT3.1mA
fs = 48 kHz, AVDD10
fs = 48 kHz, IOVDD0.1
Current consumption during active operation with IV sense enabledfs = 48 kHz, VBAT3.1mA
fs = 48 kHz, AVDD12.5
fs = 48 kHz, IOVDD0.1
PEAK VOLTAGE LIMITER
Limiter maximum threshold214.7V
Limiter minimum threshold214.7V
Limiter inflection point214.7V
Limiter VBAT tracking slope14V/V
Limiter max attenuation116.5dB
Limiter latencyTime from VBAT dipping below threshold to initial gain reduction23µs
Limiter attack rate5640µs/step
Limiter attack step size0.252dB/step
Limiter hold time01000ms
Limiter release rate101500ms/step
Limiter release step size0.252dB/step
BROWN OUT PREVENTION LIMITER
Brownout prevention threshold4.510.875V
Brownout prevention threshold step size25mV
Brownout prevention threshold toleranceMeasured at VBAT of 5V and 10V±25mV
Brownout prevention latencyTime from VBAT dipping below threshold to initial gain reduction20µs
Brownout prevention attack rate5640µs/step
Brownout prevention attack step size0.52dB/step
Brownout prevention hold time01000ms
Brownout prevention release rate101500ms/step
Brownout prevention release step size0.252dB/step