SLASF99 December 2023 TAS5827
PRODUCTION DATA
Table 6-6 lists the memory-mapped registers for the reg_map registers. All register offset addresses not listed in Table 6-6 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
1h | RESET_CTRL | Reset control | Go |
2h | DEVICE_CTRL1 | Device control 1 | Go |
3h | DEVICE_CTRL2 | Device control 2 | Go |
4h | PVDD_UV_CONTROL | PVDD UV Control | Go |
Fh | I2C_PAGE_AUTO_INC | I2C DSP memory access page auto increment | Go |
28h | SIG_CH_CTRL | Signal chain control | Go |
29h | CLOCK_DET_CTRL | Clock detection control | Go |
30h | SDOUT_SEL | SDOUT selection | Go |
31h | I2S_CTRL | I2S control 0 | Go |
33h | SAP_CTRL1 | I2S control 1 | Go |
34h | SAP_CTRL2 | I2S control 2 | Go |
35h | SAP_CTRL3 | I2S control 3 | Go |
37h | FS_MON | FS monitor | Go |
38h | BCLK_MON | BCLK monitor | Go |
39h | CLKDET_STATUS | Clock detection status | Go |
40h | DSP_PGM_MODE | DSP program mode | Go |
46h | DSP_CTRL | DSP control | Go |
4Ch | DIG_VOL_LEFT | Left digital volume | Go |
4Dh | DIG_VOL_RIGHT | Right digital volume | Go |
4Eh | DIG_VOL_CTRL2 | Digital volume control 2 | Go |
4Fh | DIG_VOL_CTRL3 | Digital volume control 3 | Go |
50h | AUTO_MUTE_CTRL | Auto mute control | Go |
51h | AUTO_MUTE_TIME | Auto mute time | Go |
53h | ANA_CTRL | Analog control | Go |
54h | AGAIN | Analog gain | Go |
5Eh | ADC_RPT | ADC(PVDD voltage) report | Go |
60h | GPIO_CTRL | GPIO control | Go |
61h | GPIO0_SEL | GPIO0 output selection | Go |
62h | GPIO1_SEL | GPIO1 output selection | Go |
63h | GPIO2_SEL | GPIO2 output selection | Go |
64h | GPIO_INPUT_SEL | GPIO input selection | Go |
65h | MISC_CTRL1 | misc control 1 | Go |
66h | MISC_CTRL2 | misc control 2 | Go |
67h | DIE_ID | DIE ID | Go |
68h | POWER_STATE | Power State | Go |
69h | AUTOMUTE_STATE | Auto mute state | Go |
6Ah | RAMP_PHASE_CTRL | Switching clock phase control | Go |
6Bh | RAMP_SS_CTRL0 | Spread spectrum control 0 | Go |
6Ch | RAMP_SS_CTRL1 | Spread spectrum control 1 | Go |
70h | CHAN_FAULT | Channel fault | Go |
71h | GLOBAL_FAULT1 | Global fault 1 | Go |
72h | GLOBAL_FAULT2 | Global fault 2 | Go |
73h | WARNING | Warning | Go |
74h | PIN_CONTROL1 | Pin control 1 | Go |
75h | PIN_CONTROL2 | Pin control 2 | Go |
76h | MISC_CONTROL3 | MISC control 3 | Go |
77h | CBC_CONTROL | CBC control | Go |
78h | FAULT_CLEAR | Fault clear | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
RESET_CTRL is shown in Figure 6-18 and described in Table 6-8.
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Reset control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RST_MOD | RESERVED | RST_REG | ||||
W-0h | W-0h | W-0h | W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | W | 0h | |
4 | RST_MOD | W | 0h | WRITE CLEAR BIT Reset Modules This bit
resets the interpolation filter and the DAC modules.
Since the DSP is also reset, the coefficient RAM
content will also be cleared by the DSP. This bit is
auto cleared and can be set only in Hi-Z mode. 0: Normal 1: Reset modules |
3-1 | RESERVED | W | 0h | |
0 | RST_REG | W | 0h | WRITE CLEAR BIT Reset Registers This bit
resets the mode registers back to their initial
values. The RAM content is not cleared. This bit is
auto cleared and must be set only when the DAC is in
Hi-Z mode (resetting registers when the DAC is
running is prohibited and not supported). 0: Normal 1: Reset mode registers |
DEVICE_CTRL1 is shown in Figure 6-19 and described in Table 6-9.
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Device control 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FSW_SEL | RESERVED | PBTL_MODE | MODULATION | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6-4 | FSW_SEL | R/W | 0h | Select PWM switching frequency(Fsw) 3'b 000:384kHz 3'b 010:480kHz 3'b 011:576kHz 3'b 100:768kHz 3'b 101:1.024MHz Others reserved |
3 | RESERVED | R/W | 0h | |
2 | PBTL_MODE | R/W | 0h | 0: Set device to BTL mode
1:Set device to PBTL mode |
1-0 | MODULATION | R/W | 0h | 00:BD mode
01:1SPW mode 10:Hybrid mode 11: Reserved |
DEVICE_CTRL2 is shown in Figure 6-20 and described in Table 6-10.
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Device control 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DSP_RST | CH1_MUTE | CH2_MUTE | STATE_CTL | |||
R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R/W | 0h | |
4 | DSP_RST | R/W | 1h | DSP reset When the bit is made 0, DSP will start powering up and send out data. This needs to be made 0 only after all the input clocks are settled so that DMA channels do not go out of sync. 0: Normal operation 1: Reset the DSP |
3 | CH1_MUTE | R/W | 0h | Mute Channel 1 This bit issues soft mute request for the ch1. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute |
2 | CH2_MUTE | R/W | 0h | Mute Channel 2 This bit issues soft mute request for the ch2. The volume will be smoothly ramped down/up to avoid pop/click noise. 0: Normal volume 1: Mute |
1-0 | STATE_CTL | R/W | 0h | Device state control register 00: Deep Sleep 01: Sleep 10: Hi-Z 11: PLAY |
PVDD_UV_CONTROL is shown in Figure 6-21 and described in Table 6-11.
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PVDD UV Control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | UV_SEQ | UV_AVG | UV_BYP | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3 | UV_SEQ | R/W | 0h | 0: Disable when have PVDD UV, device
jump to Hi-Z
1: Enable when have PVDD UV, device jump to Hi-Z |
2-1 | UV_AVG | R/W | 0h | 00: cycle by cycle, no average
01: 16 samples 10: 32 samples 11: 64 samples |
0 | UV_BYP | R/W | 0h | 0: Disable PVDD drop function
1: Enable PVDD drop function |
I2C_PAGE_AUTO_INC is shown in Figure 6-22 and described in Table 6-12.
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I2C DSP memory access page auto increment
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PAGE_INC | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3 | PAGE_INC | R/W | 0h | Page auto increment disable Disable page auto increment mode. for non-zero books. When end of page is reached it goes back to 8th address location of next page when this bit is 0. When this bit is 1 it goes to 0 th location of current page itself like in older part. 0: Enable Page auto increment 1: Disable Page auto increment |
2-0 | RESERVED | R/W | 0h |
SIG_CH_CTRL is shown in Figure 6-23 and described in Table 6-13.
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Signal chain control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCLK_RATIO | FS_MODE | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | BCLK_RATIO | R/W | 0h | These bits indicate the configured BCLK
ratio, the number of BCLK clocks in one audio frame.
4'b0000: Auto detection 4'b0011:32FS 4'b0101:64FS 4'b0111:128FS 4'b1001:256FS 4'b1011:512FS Others reserved. |
3-0 | FS_MODE | R/W | 0h | FS Speed Mode These bits select the FS
operation mode, which must be set according to the
current audio sampling rate. 4’b0000 Auto detection 4’b0010 8kHz 4’b0100 16kHz 4’b0110 32kHz 4’b1000 44.1kHz 4’b1001 48kHz 4'b1010 88.2kHz 4’b1011 96kHz 4’b1100 176.4kHz 4’b1101 192kHz Others Reserved |
CLOCK_DET_CTRL is shown in Figure 6-24 and described in Table 6-14.
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Clock detection control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DET_PLL | BCLK_RANGE | DET_FS | DET_BCLK | DET_BCLKMISS | RESERVED | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6 | DET_PLL | R/W | 0h | Ignore PLL overate Detection This bit controls whether to ignore the PLL overrate detection. The PLL must be slow than 150MHz or an error will be reported. When ignored, a PLL overrate error will not cause a clock error. 0: Regard PLL overrate detection 1: Ignore PLL overrate detection |
5 | BCLK_RANGE | R/W | 0h | Ignore BCLK Range Detection This bit controls whether to ignore the BCLK range detection. The BCLK must be stable between 256kHz and 50MHz or an error will be reported. When ignored, a BCLK range error will not cause a clock error. 0: Regard BCLK Range detection 1: Ignore BCLK Range detection |
4 | DET_FS | R/W | 0h | Ignore FS Error Detection This bit controls whether to ignore the FS Error detection. When ignored, FS error will not cause a clock error. But CLKDET_STATUS will report fs error. 0: Regard FS detection 1: Ignore FS detection |
3 | DET_BCLK | R/W | 0h | Ignore BCLK Detection This bit controls whether to ignore the BCLK detection against LRCLK. The BCLK must be stable between 32FS and 512FS inclusive or an error will be reported. When ignored, a BCLK error will not cause a clock error. 0: Regard BCLK detection 1: Ignore BCLK detection |
2 | DET_BCLKMISS | R/W | 0h | Ignore BCLK Missing Detection This bit controls whether to ignore the BCLK missing detection. When ignored an BCLK missing will not cause a clock error. 0: Regard BCLK missing detection 1: Ignore BCLK missing detection |
1-0 | RESERVED | R/W | 0h |
SDOUT_SEL is shown in Figure 6-25 and described in Table 6-15.
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SDOUT selection
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SDOUT_SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | RESERVED | R/W | 0h | |
0 | SDOUT_SEL | R/W | 0h | SDOUT Select This bit selects what is being output as SDOUT via GPIO pins. 0: SDOUT is the DSP output (post-processing) 1: SDOUT is the DSP input (pre-processing) |
I2S_CTRL is shown in Figure 6-26 and described in Table 6-16.
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I2S control 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BCLK_INV | RESERVED | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R/W | 0h | |
5 | BCLK_INV | R/W | 0h | BCLK Polarity This bit sets the inverted BCLK mode. In inverted BCLK mode, the DAC assumes that the LRCLK and DIN edges are aligned to the rising edge of the BCLK. Normally they are assumed to be aligned to the falling edge of the BCLK. 0: Normal BCLK mode 1: Inverted BCLK mode |
4-0 | RESERVED | R/W | 0h |
SAP_CTRL1 is shown in Figure 6-27 and described in Table 6-17.
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I2S control 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2SSHIFT_MSB | RESERVED | DATA_FMT | LRCLK_PULSE | FRAME_LENGTH | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-2h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | I2SSHIFT_MSB | R/W | 0h | I2S Shift MSB. Combine with the 8 bits in low register 34h. |
6 | RESERVED | R/W | 0h | |
5-4 | DATA_FMT | R/W | 0h | I2S Data Format These bits control both input and output audio interface formats for DAC operation. 00: I2S 01: DSP/TDM 10: RTJ 11: LTJ |
3-2 | LRCLK_PULSE | R/W | 0h | If the LRCLK pulse is shorter than 8 x
BCLK, set bit 0-1 to '01' Otherwise, keep these bits as default value '00' 00: High width of LRCLK pulse is equal or greater than 8 cycles of BCLK 01: High width of LRCLK pulse is less than 8 cycles of BCLK |
1-0 | FRAME_LENGTH | R/W | 2h | I2S Word Length These bits control both input and output audio interface sample word lengths for DAC operation. 00: 16 bits 01: 20 bits 10: 24 bits 11: 32 bits |
SAP_CTRL2 is shown in Figure 6-28 and described in Table 6-18.
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I2S control 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I2SSHIFT_LSB | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | I2SSHIFT_LSB | R/W | 0h | I2S Shift LSB These bits control the offset of audio data in the audio frame for both input and output. The offset is defined as the number of BCLK from the starting (MSB) of audio frame to the starting of the desired audio sample. 8'b00000000: offset = 0 BCLK (no offset) 8'b00000001: ofsset = 1 BCLK 8'b00000010: offset = 2 BCLKs … 8'b11111111: offset = 512 BCLKs |
SAP_CTRL3 is shown in Figure 6-29 and described in Table 6-19.
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I2S control 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_DAC | RESERVED | CH2_DAC | ||||
R/W-0h | R/W-1h | R/W-0h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R/W | 0h | |
5-4 | CH1_DAC | R/W | 1h | Channel 1 DAC Data Path These bits
control the channel 1 audio data path connection.
00: Zero data (mute) 01: Ch1 data 10: Ch2 data 11: Reserved (do not set) |
3-2 | RESERVED | R/W | 0h | |
1-0 | CH2_DAC | R/W | 1h | Channel 2 DAC Data Path These bits
control the channel 2 audio data path connection.
00: Zero data (mute) 01: Ch2 data 10: Ch1 data 11: Reserved (do not set) |
FS_MON is shown in Figure 6-30 and described in Table 6-20.
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FS monitor
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BCLKRATIO_MSB | FS_MON | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | |
5-4 | BCLKRATIO_MSB | R | 0h | 2 MSB of detected BCLK ratio. These bits indicate the currently detected BCLK ratio, the number of BCLK clocks in one audio frame. Combine with the 8 bits in low register 38h. BCLK = 32 FS~512 FS |
3-0 | FS_MON | R | 0h | These bits indicate the currently
detected audio sampling rate. 4’b0000 FS Error 4’b0010 8kHz 4’b0100 16kHz 4’b0110 32kHz 4’b1000 Reserved 4’b1001 48kHz 4’b1011 96kHz 4’b1101 192kHz Others Reserved |
BCLK_MON is shown in Figure 6-31 and described in Table 6-21.
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BCLK monitor
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BCLKRATIO_LSB | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | BCLKRATIO_LSB | R | 0h | These bits indicate the currently
detected BCLK ratio, the number of BCLK clocks in
one audio frame. BCLK = 32 FS~512 FS |
CLKDET_STATUS is shown in Figure 6-32 and described in Table 6-22.
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Clock detection status
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BCLK_OVERRATE | PLL_OVERRATE | PLL_LOCKED | BCLK_MISSING | BCLK_VALID | FS_VALID | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | |
5 | BCLK_OVERRATE | R | 0h | This bit indicates whether the BCLK is
overrate or underrate. 0: BCLK is underrate 1: BCLK is overrate |
4 | PLL_OVERRATE | R | 0h | This bit indicates whether the PLL is
overrate or not. 0: PLL is underrate 1: PLL is overrate |
3 | PLL_LOCKED | R | 0h | This bit indicates whether the PLL is
locked or not. The PLL will be reported as unlocked
when it is disabled. 0: PLL is locked 1: PLL is not locked |
2 | BCLK_MISSING | R | 0h | This bit indicates whether the BCLK is
missing or not. 0: BCLK is normal 1: BCLK is missing |
1 | BCLK_VALID | R | 0h | This bit indicates whether the BCLK is
valid or not. The BCLK ratio must be stable and in
the range of 32-512FS to be valid. 0: BCLK is valid 1: BCLK is not valid |
0 | FS_VALID | R | 0h | In auto detection
mode(reg_fsmode=0),this bit indicated whether the
audio sampling rate is valid. In non auto detection
mode(reg_fsmode!=0), FS error indicates that
configured sampling frequency set by LRCLK(FS) is
different with detected sampling frequency. Even if
FS Error Detection Ignore is set, this flag will be
also asserted. 0: Sampling rate is valid 1: Not valid |
DSP_PGM_MODE is shown in Figure 6-33 and described in Table 6-23.
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DSP program mode
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_HIZ | CH2_HIZ | DSP_MODE | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3 | CH1_HIZ | R/W | 0h | 1: Force CH1 to Hi-Z mode 0: Normal operation |
2 | CH2_HIZ | R/W | 0h | 1: Force CH2 to Hi-Z mode 0: Normal operation |
1-0 | DSP_MODE | R/W | 1h | DSP Program Selection These bits select the DSP program to use for audio processing. 00: RAM mode 01: ROM mode Others reserved. |
DSP_CTRL is shown in Figure 6-34 and described in Table 6-24.
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DSP control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PROC_RATE | RESERVED | IRAM_BOOT | DEF_COEF | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R/W | 0h | |
4-3 | PROC_RATE | R/W | 0h | 00:input 01:48kHz 10:96kHz 11:192kHz |
2 | RESERVED | R/W | 0h | |
1 | IRAM_BOOT | R/W | 0h | DSP boots from IRAM When set DSP will boot from IRAM instead of IROM 0: Boot DSP from IROM 1: Boot DSP from IRAM |
0 | DEF_COEF | R/W | 1h | Use default coefficients from ZROM This bit controls whether to use default coefficients from ZROM or use the non-default coefficients downloaded to device by the Host 0 : Don't use default coefficients from ZROM 1 : Use default coefficents from ZROM |
DIG_VOL_LEFT is shown in Figure 6-35 and described in Table 6-25.
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Left digital volume
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH1_PGA | |||||||
R/W-30h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH1_PGA | R/W | 30h | Channel 1 Volume These bits control the ch1 digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. 8'b00000000: +24.0 dB 8'b00000001: +23.5 dB … 8'b00101111: +0.5 dB 8'b00110000: 0.0 dB 8'b00110001: -0.5 dB ... 8'b11111110: -103 dB 8'b11111111: Mute |
DIG_VOL_RIGHT is shown in Figure 6-36 and described in Table 6-26.
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Right digital volume
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH2_PGA | |||||||
R/W-30h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | CH2_PGA | R/W | 30h | Channel 2 Volume These bits control the ch2 digital volume. The digital volume is 24 dB to -103 dB in -0.5 dB step. 8'b00000000: +24.0 dB 8'b00000001: +23.5 dB … 8'b00101111: +0.5 dB 8'b00110000: 0.0 dB 8'b00110001: -0.5 dB ... 8'b11111110: -103 dB 8'b11111111: Mute |
DIG_VOL_CTRL2 is shown in Figure 6-37 and described in Table 6-27.
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Digital volume control 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VNUS | VNUF | VNDS | VNDF | ||||
R/W-0h | R/W-3h | R/W-0h | R/W-3h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VNUS | R/W | 0h | Digital Volume Normal Ramp Down
Frequency These bits control the frequency of the digital volume updates when the volume is ramping down 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute) |
5-4 | VNUF | R/W | 3h | Digital Volume Normal Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update |
3-2 | VNDS | R/W | 0h | Digital Volume Normal Ramp Up Frequency
These bits control the frequency of the digital volume updates when the volume is ramping up 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly restore the volume (Instant unmute) |
1-0 | VNDF | R/W | 3h | Digital Volume Normal Ramp Up Step These bits control the step of the digital volume updates when the volume is ramping up 00: Increment by 4 dB for each update 01: Increment by 2 dB for each update 10: Increment by 1 dB for each update 11: Increment by 0.5 dB for each update |
DIG_VOL_CTRL3 is shown in Figure 6-38 and described in Table 6-28.
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Digital volume control 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VEDS | VEDF | RESERVED | |||||
R/W-0h | R/W-3h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | VEDS | R/W | 0h | Digital Volume Emergency Ramp Down
Frequency These bits control the frequency of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute 00: Update every 1 FS period 01: Update every 2 FS periods 10: Update every 4 FS periods 11: Directly set the volume to zero (Instant mute) |
5-4 | VEDF | R/W | 3h | Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute 00: Decrement by 4 dB for each update 01: Decrement by 2 dB for each update 10: Decrement by 1 dB for each update 11: Decrement by 0.5 dB for each update |
3-0 | RESERVED | R/W | 0h |
AUTO_MUTE_CTRL is shown in Figure 6-39 and described in Table 6-29.
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Auto mute control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AM_CTL | AMUTE_CH2 | AMUTE_CH1 | ||||
R/W-0h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R/W | 0h | |
2 | AM_CTL | R/W | 1h | 0: Auto mute ch1 and ch2 independently
1: Auto mute ch1 and ch2 only when both channels are about to be auto muted |
1 | AMUTE_CH2 | R/W | 1h | Auto Mute Channel 2 This bit enables or disables auto mute on Channel 2 0: Disable Channel 2 auto mute 1: Enable Channel 2 auto mute |
0 | AMUTE_CH1 | R/W | 1h | Auto Mute Channel 1 This bit enables or disables auto mute on Channel 1 0: Disable Channel 1 auto mute 1: Enable Channel 1 auto mute |
AUTO_MUTE_TIME is shown in Figure 6-40 and described in Table 6-30.
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Auto mute time
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_AMT | RESERVED | CH2_AMT | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6-4 | CH1_AMT | R/W | 0h | Auto Mute Time for Channel 1 These bits specify the length of consecutive zero samples at ch1 before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec |
3 | RESERVED | R/W | 0h | |
2-0 | CH2_AMT | R/W | 0h | Auto Mute Time for Channel 2 These bits specify the length of consecutive zero samples at ch2 before the channel can be auto muted. The times shown are for 96 kHz sampling rate and will scale with other rates. 000: 11.5 ms 001: 53 ms 010: 106.5 ms 011: 266.5 ms 100: 0.535 sec 101: 1.065 sec 110: 2.665 sec 111: 5.33 sec |
ANA_CTRL is shown in Figure 6-41 and described in Table 6-31.
Return to the Summary Table.
Analog control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BW_CTL | RESERVED | PHASE_CTL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6-5 | BW_CTL | R/W | 0h | Class D Loop Bandwidth 00: 100kHz 01: 80kHz 10: 120kHz 11: 175kHz When Fsw=384kHz, 100kHz bandwidth is selected for high audio performance. With Fsw=768kHz, 175kHz bandwidth should be selected for high audio performance. |
4-1 | RESERVED | R/W | 0h | |
0 | PHASE_CTL | R/W | 0h | 0: Out of phase
1: In phase |
AGAIN is shown in Figure 6-42 and described in Table 6-32.
Return to the Summary Table.
Analog gain
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AGAIN | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R/W | 0h | |
4-0 | AGAIN | R/W | 0h | Analog Gain Control This bit controls the analog gain 00000: 0 dB 00001:-0.5 dB …… 11111: -15.5 dB |
ADC_RPT is shown in Figure 6-43 and described in Table 6-33.
Return to the Summary Table.
ADC(PVDD voltage) report
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PVDD_RPT | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PVDD_RPT | R | 0h | PVDD ADC reading. Each LSB means
0.12V For PVDD = 12V, the AD data = 8'b 01100100 For PVDD = 24V, the AD data = 8'b 11001000 |
GPIO_CTRL is shown in Figure 6-44 and described in Table 6-34.
Return to the Summary Table.
GPIO control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO2OE | GPIO1OE | GPIO0OE | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R/W | 0h | |
2 | GPIO2OE | R/W | 0h | GPIO2 Output Enable This bit sets the
direction of the GPIO2 pin 0: GPIO2 is input 1: GPIO2 is output |
1 | GPIO1OE | R/W | 0h | GPIO1 Output Enable This bit sets the
direction of the GPIO1 pin 0: GPIO1 is input 1: GPIO1 is output |
0 | GPIO0OE | R/W | 0h | GPIO0 Output Enable This bit sets the
direction of the GPIO0 pin 0: GPIO0 is input 1: GPIO0 is output |
GPIO0_SEL is shown in Figure 6-45 and described in Table 6-35.
Return to the Summary Table.
GPIO0 output selection
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO0SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3-0 | GPIO0SEL | R/W | 0h | 4'b0000: off (low)
4'b1000: GPIO0 as WARNZ output 4'b1011: GPIO0 as FAULTZ output 4'b1100: GPIO0 as PVDD_DROP_DETECTION 4'b1101: GPIO0 as Serial audio interface data output (SDOUT) 4'b1110: GPIO0 as RAMP clk Others reserved |
GPIO1_SEL is shown in Figure 6-46 and described in Table 6-36.
Return to the Summary Table.
GPIO1 output selection
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO1SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3-0 | GPIO1SEL | R/W | 0h | 0000: off (low)
1000: GPIO1 as WARNZ output 1011: GPIO1 as FAULTZ output 1100: GPIO1 as PVDD_UV_DETECTION 1101: GPIO1 as Serial audio interface data output (SDOUT) 1110: GPIO1 as RAMP clk Others reserved |
GPIO2_SEL is shown in Figure 6-47 and described in Table 6-37.
Return to the Summary Table.
GPIO2 output selection
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO2_SEL | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3-0 | GPIO2_SEL | R/W | 0h | 4'b0000: off (low) 4'b1000: GPIO2 as WARNZ output 4'b1011: GPIO2 as FAULTZ output 4'b1100: GPIO2 as PVDD_DROP_DETECTION 4'b1101: GPIO2 as Serial audio interface data output (SDOUT) 4'b1110: GPIO2 as RAMP clk 4'b1111: Reserved |
GPIO_INPUT_SEL is shown in Figure 6-48 and described in Table 6-38.
Return to the Summary Table.
GPIO input selection
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIOSYNC_SEL | GPIORST_SEL | GPIOM_SEL | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R/W | 0h | |
5-4 | GPIOSYNC_SEL | R/W | 0h | 00: N/A
01: GPIO0 10: GPIO1 11: GPIO2 |
3-2 | GPIORST_SEL | R/W | 0h | 00: N/A 01: GPIO0 10: GPIO1 11: GPIO2 |
1-0 | GPIOM_SEL | R/W | 0h | 00: N/A 01: GPIO0 10: GPIO1 11: GPIO2 |
MISC_CTRL1 is shown in Figure 6-49 and described in Table 6-39.
Return to the Summary Table.
misc control 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO_OUTPUT | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R/W | 0h | |
2-0 | GPIO_OUTPUT | R/W | 0h | Writing 3 bits for GPIO output |
MISC_CTRL2 is shown in Figure 6-50 and described in Table 6-40.
Return to the Summary Table.
misc control 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GPIO_INV | ||||||
R/W-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R/W | 0h | |
2-0 | GPIO_INV | R/W | 0h | Enable GPIO output invert by setting
this bit to '1' Default disable the invert function of GPIO output. |
DIE_ID is shown in Figure 6-51 and described in Table 6-41.
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DIE ID
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIE_ID | |||||||
R-A9h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIE_ID | R | A9h | Die ID for TAS5827. |
POWER_STATE is shown in Figure 6-52 and described in Table 6-42.
Return to the Summary Table.
Power State
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STATE_RPT | ||||||
R-0h | R-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 0h | |
1-0 | STATE_RPT | R | 0h | 00: Deep sleep
01: Sleep 10: Hi-Z 11: Play others: reserved |
AUTOMUTE_STATE is shown in Figure 6-53 and described in Table 6-43.
Return to the Summary Table.
Auto mute state
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH2MUTE_STATUS | CH1MUTE_STATUS | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R | 0h | |
1 | CH2MUTE_STATUS | R | 0h | This bit indicates the auto mute status
for Channel 2. 0: Not auto muted 1: Auto muted |
0 | CH1MUTE_STATUS | R | 0h | This bit indicates the auto mute status
for Channel 1. 0: Not auto muted 1: Auto muted |
RAMP_PHASE_CTRL is shown in Figure 6-54 and described in Table 6-44.
Return to the Summary Table.
Switching clock phase control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RAMPPHASE_SEL | RAMPSYNC_SEL | RAMPSYNC_EN | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R/W | 0h | |
3-2 | RAMPPHASE_SEL | R/W | 0h | Select ramp clock phase when multi
devices are integrated in one system to reduce EMI
and peak supply peak current, it is recomended set
all devices the same RAMP frequency and same spread
spectrum. it must be set before driving device into
PLAY mode if this feature is needed. 00: 0 degree 01: 45 degree 10: 90 degree 11: 135 degree all of above have a 45 degree of phase shift |
1 | RAMPSYNC_SEL | R/W | 0h | Ramp phase sync source 0: GPIO sync 1: Internal sync |
0 | RAMPSYNC_EN | R/W | 0h | 1: Enable ramp phase sync 0: Disable ramp phase sync |
RAMP_SS_CTRL0 is shown in Figure 6-55 and described in Table 6-45.
Return to the Summary Table.
Spread spectrum control 0
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDM_EN | TRI_EN | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RESERVED | R/W | 0h | |
1 | RDM_EN | R/W | 0h | 1: Random SS enable 0: Random SS disable |
0 | TRI_EN | R/W | 0h | 1: Triangle SS enable 0: Triangle SS disable |
RAMP_SS_CTRL1 is shown in Figure 6-56 and described in Table 6-46.
Return to the Summary Table.
Spread spectrum control 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDM_CTL | TRI_CTL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R/W | 0h | |
6-4 | RDM_CTL | R/W | 0h | Random SS range control For Fsw of 384kHz 3'b000: SS range +/- 0.62% 3'b010: SS range +/- 1.88% 3'b011: SS range +/- 4.38% 3'b100: SS range +/- 9.38% 3'b101: SS range +/- 19.38% Others: reserved For Fsw of 576kHz 3'b000: SS range +/- 0.95% 3'b010: SS range +/- 2.86% 3'b011: SS range +/- 6.67% 3'b100: SS range +/- 14.29% 3'b101: SS range +/- 29.52% Others: reserved |
3-0 | TRI_CTL | R/W | 0h | Triangle SS frequency and range
control 4'b0000: 24kHz SS +/- 5% 4'b0001: 24kHz SS +/- 10% 4'b0010: 24kHz SS +/- 20% 4'b0011: 24kHz SS +/- 25% 4'b0100: 48kHz SS +/- 5% 4'b0101: 48kHz SS +/- 10% 4'b0110: 48kHz SS +/- 20% 4'b0111: 48kHz SS +/- 25% 4'b1000: 32kHz SS +/- 5% 4'b1001: 32kHz SS +/- 10% 4'b1010: 32kHz SS +/- 20% 4'b1011: 32kHz SS +/- 25% 4'b1100: 16kHz SS +/- 5% 4'b1101: 16kHz SS +/- 10% 4'b1110: 16kHz SS +/- 20% 4'b1111: 16kHz SS +/- 25% |
CHAN_FAULT is shown in Figure 6-57 and described in Table 6-47.
Return to the Summary Table.
Channel fault
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1DC | CH2DC | CH1OC | CH2OC | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RESERVED | R | 0h | |
3 | CH1DC | R | 0h | Channel 1 DC fault. Once there is a DC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
2 | CH2DC | R | 0h | Channel 2 DC fault. Once there is a DC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
1 | CH1OC | R | 0h | Channel 1 over current fault. Once there is a OC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
0 | CH2OC | R | 0h | Channel 2 over current fault. Once there is a OC fault, the fault is latched and this bit is set to be 1. Class D output is set to Hi-Z. Report by FAULT pin (GPIO). Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
GLOBAL_FAULT1 is shown in Figure 6-58 and described in Table 6-48.
Return to the Summary Table.
Global fault 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BQWRTFAULT_FLAG | EEPROMFAULT_FLAG | RESERVED | CLKFAULT_FLAG | PVDDOV_FLAG | PVDDUV_FLAG | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RESERVED | R | 0h | |
6 | BQWRTFAULT_FLAG | R | 0h | 0: The recent BQ is written
successfully 1: The recent BQ writed failed |
5 | EEPROMFAULT_FLAG | R | 0h | 0: EEPROM boot load was done
successfully 1: EEPROM boot load was done unsuccessfully |
4-3 | RESERVED | R | 0h | |
2 | CLKFAULT_FLAG | R | 0h | Clock fault. Once there is a Clock
fault, the fault is latched and this bit is set to
be 1. Class D output is set to Hi-Z. Report by FAULT
pin (GPIO). Clock fault works with an auto-recovery mode, once the clock error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
1 | PVDDOV_FLAG | R | 0h | PVDD OV fault. Once there is a OV fault,
the fault is latched and this bit is set to be 1.
Class D output is set to Hi-Z. Report by FAULT pin
(GPIO). OV fault works with an auto-recovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
0 | PVDDUV_FLAG | R | 0h | PVDD UV fault. Once there is a UV fault,
the fault is latched and this bit is set to be 1.
Class D output is set to Hi-Z. Report by FAULT pin
(GPIO). UV fault works with an auto-recovery mode, once the UV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
GLOBAL_FAULT2 is shown in Figure 6-59 and described in Table 6-49.
Return to the Summary Table.
Global fault 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH2CBC_FLAG | CH1CBC_FLAG | OTSD_FLAG | ||||
R-0h | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RESERVED | R | 0h | |
2 | CH2CBC_FLAG | R | 0h | 0: No CBC fault on Channel 2 1: CBC fault triggered on Channel 2 |
1 | CH1CBC_FLAG | R | 0h | 0: No CBC fault on Channel 1 1: CBC fault triggered on Channel 1 |
0 | OTSD_FLAG | R | 0h | Over temperature shut down fault Once
there is a OT fault, the fault is latched and this
bit is set to be 1. Class D output is set to Hi-Z.
Report by FAULT pin (GPIO). OV fault works with an autorecovery mode, once the OV error removes, device automatically returns to the previous state. Clear this fault by setting bit 7 of Fault_clear Register (78h) to 1 or this bit keeps 1. |
WARNING is shown in Figure 6-60 and described in Table 6-50.
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Warning
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1CBCW_FLAG | CH2CBCW_FLAG | OTW4_FLAG | OTW3_FLAG | OTW2_FLAG | OTW1_FLAG | |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | RESERVED | R | 0h | |
5 | CH1CBCW_FLAG | R | 0h | 0: No CBC warning on Channel 1 1: CBC warning triggered on Channel 1 |
4 | CH2CBCW_FLAG | R | 0h | 0: No CBC warning on Channel 2 1: CBC warning triggered on Channel 2 |
3 | OTW4_FLAG | R | 0h | 0: No temperature level 4
warning 1: Over temperature warning level 4 is triggered |
2 | OTW3_FLAG | R | 0h | 0: No temperature level 3
warning 1: Over temperature warning level 3 is triggered |
1 | OTW2_FLAG | R | 0h | 0: No temperature level 2
warning 1: Over temperature warning level 2 is triggered |
0 | OTW1_FLAG | R | 0h | 0: No temperature level 1
warning 1: Over temperature warning level 1 is triggered |
PIN_CONTROL1 is shown in Figure 6-61 and described in Table 6-51.
Return to the Summary Table.
Pin control 1
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASK_OTSD | MASK_DVDDUV | MASK_DVDDOV | MASK_CLKERROR | MASK_PVDDUV | MASK_PVDDOV | MASK_DC | MASK_OC |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MASK_OTSD | R/W | 0h | 0: Enable OTSD fault report 1: Mask OTSD fault report |
6 | MASK_DVDDUV | R/W | 0h | 0: Enable DVDD UV fault report 1: Mask DVDD UV report |
5 | MASK_DVDDOV | R/W | 0h | 0: Enable DVDD OV fault report 1: Mask DVDD OV fault report |
4 | MASK_CLKERROR | R/W | 0h | 0: Enable CLK fault report 1: Mask CLK fault report |
3 | MASK_PVDDUV | R/W | 0h | 0: Enable UV fault report 1: Mask UV fault report |
2 | MASK_PVDDOV | R/W | 0h | 0: Enable OV fault report 1: Mask OV fault report |
1 | MASK_DC | R/W | 0h | 0: Enable DC fault report 1: Mask DC fault report |
0 | MASK_OC | R/W | 0h | 0: Enable OC fault report 1: Mask OC fault report |
PIN_CONTROL2 is shown in Figure 6-62 and described in Table 6-52.
Return to the Summary Table.
Pin control 2
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CBCFAULTLATCH_EN | CBCWARNLATCH_EN | CLKFAULTLATCH_EN | OTSDLATCH_EN | OTWLATCH_EN | MASK_OTW | MASK_CBCWARN | MASK_CBCFAULT |
R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-1h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CBCFAULTLATCH_EN | R/W | 1h | 0: Disable CBC fault latch 1: Enable CBC fault latch |
6 | CBCWARNLATCH_EN | R/W | 1h | 0: Disable CBC warning latch 1: Enable CBC warning latch |
5 | CLKFAULTLATCH_EN | R/W | 1h | 0: Disable CLK fault latch 1: Enable CLK fault latch |
4 | OTSDLATCH_EN | R/W | 1h | 0: Disable OTSD fault latch 1: Enable OTSD fault latch |
3 | OTWLATCH_EN | R/W | 1h | 0: Disable OTW warning latch 1: Enable OTW warning latch |
2 | MASK_OTW | R/W | 0h | 0: Enable OTW warning report 1: Mask OTW warning report |
1 | MASK_CBCWARN | R/W | 0h | 0: Enable CBC warning report 1: Mask CBC warning report |
0 | MASK_CBCFAULT | R/W | 0h | 0: Enable CBC fault report 1: Mask CBC fault report |
MISC_CONTROL3 is shown in Figure 6-63 and described in Table 6-53.
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MISC control 3
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLKDET_LATCH | RESERVED | OTSD_AUTOREC | RESERVED | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CLKDET_LATCH | R/W | 0h | 1:Latch clock detection status 0:No latch clock detection status |
6-5 | RESERVED | R/W | 0h | |
4 | OTSD_AUTOREC | R/W | 0h | 0: Disable OTSD auto recovery 1: Enable OTSD auto recovery |
3-0 | RESERVED | R/W | 0h |
CBC_CONTROL is shown in Figure 6-64 and described in Table 6-54.
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CBC control
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CBCLEVEL_SEL | CBC_EN | CBCWARN_EN | CBCFAULT_EN | |||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RESERVED | R/W | 0h | |
4-3 | CBCLEVEL_SEL | R/W | 0h | These bits set Cycle-By-Cycle current
limiting level, which is a percentage of the
Over-Current Threshold: 2b'00: 80% 2b'10: 60% 2b'01: 40% 2b'11: reserved |
2 | CBC_EN | R/W | 0h | 0: Disable CBC function 1: Enable CBC function |
1 | CBCWARN_EN | R/W | 0h | 0: Disable CBC warning 1: Enable CBC warning |
0 | CBCFAULT_EN | R/W | 0h | 0: Disable CBC fault
1: Enable CBC fault |
FAULT_CLEAR is shown in Figure 6-65 and described in Table 6-55.
Return to the Summary Table.
Fault clear
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAULT_CLR | RESERVED | ||||||
W-0h | W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | FAULT_CLR | W | 0h | WRITE CLEAR BIT 0: No fault clear 1: Clear analog fault |
6-0 | RESERVED | W | 0h |