SLASF99A December   2023  – November 2025 TAS5827

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Clock Halt Auto-recovery
      5. 6.3.5 Sample Rate on the Fly Change
      6. 6.3.6 Serial Audio Port - Data Formats and Bit Depths
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
        2. 6.4.2.2 PBTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 6.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 6.4.3.3.2 Phase Synchronization With GPIO
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
      7. 6.4.7 Programming and Control
        1. 6.4.7.1 I2C Serial Communication Bus
        2. 6.4.7.2 Hardware Control Mode
        3. 6.4.7.3 I2C Target Address
          1. 6.4.7.3.1 Random Write
          2. 6.4.7.3.2 Sequential Write
          3. 6.4.7.3.3 Random Read
          4. 6.4.7.3.4 Sequential Read
          5. 6.4.7.3.5 DSP Memory Book, Page and BQ update
          6. 6.4.7.3.6 Checksum
            1. 6.4.7.3.6.1 Cyclic Redundancy Check (CRC) Checksum
            2. 6.4.7.3.6.2 Exclusive or (XOR) Checksum
        4. 6.4.7.4 Control via Software
          1. 6.4.7.4.1 Startup Procedures
          2. 6.4.7.4.2 Shutdown Procedures
        5. 6.4.7.5 Protection and Monitoring
          1. 6.4.7.5.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 6.4.7.5.2 Overcurrent Shutdown (OCSD)
          3. 6.4.7.5.3 DC Detect Error
          4. 6.4.7.5.4 Overtemperature Shutdown (OTSD)
          5. 6.4.7.5.5 PVDD Overvoltage and Undervoltage Error
          6. 6.4.7.5.6 PVDD Drop Detection
          7. 6.4.7.5.7 Clock Fault
  8. 7 Register Maps
    1. 7.1 reg_map Registers
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 2.0 (Stereo BTL) System
      2. 8.1.2 Mono (PBTL) Systems
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
        1. 8.2.1.1 General Guidelines for Audio Amplifiers
        2. 8.2.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 8.2.1.3 Optimizing Thermal Performance
          1. 8.2.1.3.1 Device, Copper, and Component Layout
          2. 8.2.1.3.2 Stencil Pattern
          3. 8.2.1.3.3 PCB footprint and Via Arrangement
          4. 8.2.1.3.4 Solder Stencil
      2. 8.2.2 Layout Example
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 DVDD Supply
      2. 8.3.2 PVDD Supply
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Free-air room temperature 25°C, 1SPW Mode, LC filter=10uH+0.68uF, Fsw=384kHz, Class D Bandwidth=80kHz, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Digital I/O
|IIH|Input logic high current level
for DVDD referenced digital
input pins		VIN(DigIn) = VDVDD10uA
|IIL|Input logic low current level
for DVDD referenced digital
input pins		VIN(DigIn) = 0V–10uA
VIH(Digin)Input logic high threshold for
DVDD referenced digital
inputs		70%VDVDD
VIL(Digin)Input logic low threshold for
DVDD referenced digital
inputs		30%VDVDD
VOH(Digin)Output logic high voltage
level		IOH = 4mA80%VDVDD
VOL(Digin)Output logic low voltage levelIOH = –4mA20%VDVDD
I2C CONTROL PORT
CL(I2C)Allowable load capacitance
for each I2C Line		400pF
fSCL(fast)Support SCL frequencyNo wait states, support both fast & fast plus mode4001000kHz
fSCL(slow)Support SCL frequencyNo wait states, slow mode100kHz
SERIAL AUDIO PORT
tDLYRequired LRCLK/FS to SCLK
rising edge delay		5ns
DSCLKAllowable SCLK duty cycle40%60%
fSSupported input sample rates32192kHz
fSCLKSupported SCLK frequencies3264fS
fSCLKSCLK frequency24.576MHz
AMPLIFIER OPERATING MODE AND DC PRAMETERS
ICCQuiescent supply current of
DVDD		PDN = 2V, DVDD = 3.3V, Play mode,
General Audio Process flow with full DSP running		23mA
ICCQuiescent supply current of
DVDD		PDN = 2V, DVDD = 3.3V,Sleep mode1mA
ICCQuiescent supply current of
DVDD		PDN = 2V, DVDD = 3.3V,Deep Sleep mode1mA
ICCQuiescent supply current of
DVDD		PDN = 0.8V, DVDD = 3.3V,Shutdown mode16uA
ICCQuiescent supply current of
PVDD		PDN = 2V, PVDD = 18V, No Load, LC filter =
10μH + 0.68μF, FSW = 384kHz, 1SPW Modulation, Play Mode		39mA
ICCQuiescent supply current of
PVDD		PDN = 2 V, PVDD = 18V, No Load, LC filter =
10μH + 0.68μF, FSW = 384kHz, Output Hi-Z Mode		11mA
ICCQuiescent supply current of
PVDD		PDN = 2V, PVDD = 18V, No Load, LC filter =
10μH + 0.68μF, FSW = 384kHz, Sleep Mode		7.5mA
ICCQuiescent supply current of
PVDD		PDN = 2V, PVDD = 18V, No Load, LC filter =
10μH + 0.68μF, FSW = 384kHz, Deep Sleep Mode		10uA
ICCQuiescent supply current of
PVDD		PDN = 2V, PVDD = 18V, No Load, LC filter =
10μH + 0.68μF, FSW = 384kHz, Shutdown Mode		10uA
AV(SPK_AMP)Programmable GainValue represents the "peak voltage" disregarding
clipping due to lower PVDD
Measured at 0dB input(1FS)		13.7529.4dBV
ΔAV(SPK_AMP)Amplifier gain errorGain = 26.4dBV0.5dB
fSPK_AMPSwitching frequency of the
speaker amplifier. 		Software Mode384kHz
480kHz
576 kHz
768kHz
1024 kHz
Hardware Mode480kHz
768kHz
RDS(on)Drain-to-source on resistance
of the individual output
MOSFETs		FET + Metallization. VPVDD=24V, I(OUT)=500mA,
TJ=25 ℃		70mΩ
PROTECTION
OCETHRESOver-Current Error Threshold
(Speaker current)		Speaker Output Current (Post LC filter), Speaker
current, LC Filter=10 uH+0.68uF, BTL Mode		7.588.5A
UVETHRES(PVDD)PVDD under voltage error
threshold		3.744.2V
OVETHRES(PVDD)PVDD over voltage error
threshold		2728.129.2V
DCETHRESOutput DC Error protection
threshold		Class D Amplifier's output DC voltage cross
speaker load to trigger Output DC Fault protection		3.3V
TDCDETOutput DC Detect timeClass D Amplifier's output remain at or above
DCETHRES		570ms
OTETHRESOver temperature error
threshold		170℃
OTEHysteresisOver temperature error
hysteresis		10℃
OTWTHRESOver temperature warning
level		Read by register 0x73 bit0106°C
OTWTHRESOver temperature warning
level		Read by register 0x73 bit1130°C
OTWTHRESOver temperature warning
level		Read by register 0x73 bit2140°C
OTWTHRESOver temperature warning
level		Read by register 0x73 bit3154°C
AUDIO PERFORMACNE (STEREO BTL)
|VOS|Amplifier offset voltageMeasured differentially with zero input data,
programmable gain configured with 29.4dBV
analog gain, VPVDD range:12V~24V		–55mV
PO(SPK)Output Power (Per Channel)VPVDD = 18V, LC Filter=10uH+0.68uF, RSPK = 4Ω, f = 1kHz, THD+N = 10%
41W
VPVDD = 18V, LC Filter=10uH+0.68uF, RSPK = 4Ω, f = 1kHz, THD+N = 1%
33W
VPVDD = 18V, LC Filter=10uH+0.68uF, RSPK = 6Ω, f = 1kHz, THD+N = 10%
31 W
VPVDD = 18V, LC Filter=10uH+0.68uF, RSPK = 6Ω, f = 1kHz, THD+N = 1%
25 W
VPVDD = 21V, LC Filter=10uH+0.68uF, RSPK = 4Ω, f = 1kHz, THD+N = 10%
55 W
VPVDD = 21V, LC Filter=10 uH+0.68uF, RSPK = 4Ω, f = 1kHz, THD+N = 1%
45 W
VPVDD = 25V, LC Filter=10uH+0.68uF, RSPK = 6Ω, f = 1kHz, THD+N = 10%
57W
VPVDD = 25V, LC Filter=10uH+0.68uF, RSPK = 6Ω, f = 1kHz, THD+N = 1%
47W
THD+NSPKTotal harmonic distortion and
noise
(PO = 1W, f = 1kHz)		VPVDD = 18V,LC Filter=10uH+0.68uF, Load=4 Ω0.05%
VPVDD = 25V,LC Filter=10uH+0.68uF,Load=6 Ω0.03%
ICN(SPK)Idle channel noise(Aweighted,
AES17)		VPVDD = 18V, LC Filter=10uH+0.68uF, Load=4Ω, Fsw=576kHz, BD Modulation40µVrms
VPVDD = 18V, LC Filter=10uH+0.68uF, Load=4Ω, Fsw=384kHz, 1SPW Modulation35µVrms
VPVDD = 25V, LC Filter=10uH+0.68uF, Load=6Ω, Fsw=384kHz, 1SPW Modulation40µVrms
VPVDD = 25V, LC Filter=3.3uH+1uF, Load=6Ω, Fsw=1024kHz, BD Modulation37µVrms
DRDynamic rangeA-Weighted, -60dBFS method. VPVDD = 25V, Load=6 Ω, Analog Gain = 29.4dBV115dB
SNRSignal-to-noise ratioA-Weighted, referenced to 1% THD+N Output
Level, VPVDD=25V, load=6 Ω		115dB
A-Weighted, referenced to 1% THD+N Output
Level, VPVDD=18V, Load=4 Ω		115dB
PSRRPower supply rejection ratioInjected Noise = 1kHz, 1 Vrms, VPVDD = 25V,
input audio signal = digital zero		85dB
Cross-talkSPKCross-talk (worst case
between left-to-right and
right-to-left coupling)		f = 1kHz, based on Inductor (SPM10040T-100M)
from TDK		100dB
AUDIO PERFORMANCE (MONO PBTL)
|VOS|Amplifier offset voltageMeasured differentially with zero input data,
programmable gain configured with 29.4dBV
Analog gain, VPVDD = 12V-25V range,  1SPW mode		–55mV
PO(SPK)Output PowerVPVDD = 25V, RSPK = 3Ω, f = 1kHz, THD+N = 1%
94W
VPVDD = 25V, RSPK = 3Ω, f = 1kHz, THD+N = 10%
112W
VPVDD = 18V, RSPK = 2Ω, f = 1kHz, THD+N = 1%
67W
VPVDD = 18V, RSPK = 2Ω, f = 1kHz, THD+N = 10%
83W
THD+NSPKTotal harmonic distortion and
noise
(PO = 1W, f = 1kHz)		VPVDD = 18V, LC-filter=10uH+0.68uF, RSPK = 2Ω0.07%
VPVDD = 25V, LC-filter=10uH+0.68uF, RSPK = 3Ω0.05%
DRDynamic rangeA-Weighted, -60dBFS method, VPVDD=25V, RSPK
= 3Ω.		113dB
SNRSignal-to-noise ratioA-Weighted, referenced to 1% THD+N Output
Level, VPVDD=25V, RSPK = 3Ω		113dB
A-Weighted,referenced to 1% THD+N Output
Level, VPVDD=18V, RSPK = 2Ω		106dB
PSRRPower supply rejection ratioInjected Noise = 1kHz, 1 Vrms,VPVDD = 18V,
input audio signal = digital zero		80dB