SCPS267B March 2017 – February 2020 TCA9803
The system designer must first select the correct variant of the TCA980x family for the load. In order to do this, the information in Table 6 must be known. The setup in Figure 19 is used for these example design requirements.
CL is the capacitance of the bus, including the pin capacitance of each slave device connected, and the capacitance of the board trace. It is possible to estimate the bus capacitance by summing up the pin capacitances of each slave device on the node (using 10-pF per slave is a safe estimate, since this is the maximum allowed per the I2C specification), but trace capacitance requires an estimation through simulation or by getting the capacitance per unit length from the board manufacturer.
|Parameter||Description||Acceptable Range||Example Value/Target|
|CL||Load capacitance (bus capacitance) on B-side||up to 400 pF||100 pF|
|tr||Rise time||up to 300 ns||≤ 150 ns|
|VCCA||VCCA supply voltage||0.8 V-3.6 V||1.2 V|
|VCCB||VCCB supply voltage||1.65 V-3.6 V||3.3 V|
|fSCL||I2C clock frequency||400 kHz|