SLLSFQ4A September   2022  – March 2023 THVD1424

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Switching Characteristics_Duplex switching
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Device Functional Modes

THVD1424 has H/F pin which allows it to be used in half-duplex or full duplex networks. Functional operation of H/F pin is described in table.

Table 8-1 Duplex switching function table
Signal state Driver Receiver Comment
H/F = VIO Driver output pins are Y and Z Receiver input pins are Y and Z Half duplex mode: Driver and receiver share same bus pins, and device state is controlled by DE and RE pins
H/F = GND Driver output pins are Y and Z Receiver input pins are A and B Full duplex mode: This is the default state of the device in case H/F is floating.

When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input D. A logic high at D causes Y to turn high and Z to turn low. In this case, the differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse, Z turns high, Y becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground; thus, when left open, the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to VIO, thus, when left open while the driver is enabled, output Y turns high and Z turns low.

Table 8-2 Driver Function Table
INPUTENABLEOUTPUTSFUNCTION
DDEYZ
HHHLActively drive bus high
LHLHActively drive bus low
XLZZDriver disabled
XOPENZZDriver disabled by default
OPENHHLActively drive bus high by default

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB in case of full duplex mode (or VY - VZ in case of half duplex mode) is positive and higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is negative and lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH-, the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output R to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).

Table 8-3 Receiver Function Table
DIFFERENTIAL INPUTENABLEOUTPUTFUNCTION
VID = VA – VB (full duplex mode) or VY – VZ (half duplex mode)RER
VTH+ < VIDLHReceive valid bus high
VTH- < VID < VTH+L?Indeterminate bus state
VID < VTH-LLReceive valid bus low
XHZReceiver disabled
XOPENZReceiver disabled by default
Open-circuit busLHFail-safe high output
Short-circuit busLHFail-safe high output
Idle (terminated) busLHFail-safe high output