SLLSFP5 January   2024 THVD2419 , THVD2429

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings [IEC]
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Dissipation
    7. 6.7 Electrical Characteristics
    8. 6.8 Switching Characteristics_250kbps
    9. 6.9 Switching Characteristics_20Mbps
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Electrostatic Discharge (ESD) Protection
      2. 8.3.2 Electrical Fast Transient (EFT) Protection
      3. 8.3.3 Surge Protection
      4. 8.3.4 Enhanced Receiver Noise Immunity
      5. 8.3.5 Failsafe Receiver
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DRC|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Switching Characteristics_250kbps

250-kbps (THVD2419) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V , VIO = 3.3 V, unless otherwise noted. (1) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
tr, tf Differential output rise/fall time RL = 54 Ω, CL = 50 pF 
See Figure 7-3		 VCC = 3 to 3.6 V, Typical at 3.3V 400 650 1200 ns
VCC = 4.5 to 5.5 V, Typical at 5 V 500 710 1200 ns
tPHL, tPLH Propagation delay VCC = 3 to 3.6 V, Typical at 3.3V 525 750 ns
VCC = 4.5 to 5.5 V, Typical at 5 V 560 770 ns
tSK(P) Pulse skew, |tPHL – tPLH| VCC = 3 to 3.6 V, Typical at 3.3V 30 70 ns
VCC = 4.5 to 5.5 V, Typical at 5 V 30 70 ns
tPHZ, tPLZ Disable time RE = X See Figure 7-4 and Figure 7-5 33 75 ns
tPZH, tPZL Enable time RE = 0 V TBD 280 ns
RE = VIO  2 4.5 µs
tSHDN Time to shutdown RE = VIO 50 500 ns
Receiver
tr, tf Output rise/fall time CL = 15 pF See Figure 7-6 13 20 ns
tPHL, tPLH Propagation delay 850 1270 ns
tSK(P) Pulse skew, |tPHL – tPLH| 5 45 ns
tPHZ, tPLZ Disable time DE = X 30 40 ns
tPZH(1) Enable time VIO = 3 V to 3.6 V; DE = VIO See Figure 7-7 90 120 ns
VIO = 1.65 V to 1.95 V, DE = VIO TBD 130 ns
tPZL(1) VIO = 3 V to 3.6 V; DE = VIO 900 1320 ns
VIO = 1.65 V to 1.95 V; DE = VIO TBD 1320 ns
tPZH(2),
tPZL(2)		 Enable time DE = 0 V See Figure 7-8 3.3 5.4 μs
tD(OFS) Delay to enter fail-safe operation CL = 15 pF See Figure 7-9 7 11 18 μs
tD(FSO) Delay to exit fail-safe operation 540 850 1260 ns
tSHDN Time to shutdown DE = 0 V See Figure 7-8 50 500 ns
(1) A, B are driver output and receiver input terminals for Half duplex devices. A, B are RX input, Y/Z are driver output terminals for Full duplex device