SLLSFO2B December   2022  – March 2024 THVD2410V , THVD2412V , THVD2450V , THVD2452V

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_250 kbps
    9. 5.9  Switching Characteristics_1 Mbps
    10. 5.10 Switching Characteristics_20 Mbps
    11. 5.11 Switching Characteristics_50 Mbps
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 ±70 V Fault Protection
      2. 7.3.2 Integrated IEC ESD and EFT Protection
      3. 7.3.3 Driver Overvoltage and Overcurrent Protection
      4. 7.3.4 Enhanced Receiver Noise Immunity
      5. 7.3.5 Receiver Fail-Safe Operation
      6. 7.3.6 Low-Power Shutdown Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Device Functional Modes

When the driver enable pin, DE, is logic high (H), the differential outputs A/Y and B/Z follow the logic states at data input D. A logic high at D causes A/Y to turn high and B/Z to turn low. In this case, the differential output voltage defined as VOD = VA – VB is positive. When D is low (L), the output states reverse: B/Z turns high, A/Y becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant (X). The DE pin has an internal pull-down resistor to ground; thus, when left open the driver is disabled (Z = high-impedance) by default. The D pin has an internal pull-up resistor to VIO; thus, when left open while the driver is enabled, output A/Y turns high and B/Z turns low.

Table 7-1 Driver Function Table
INPUTENABLEOUTPUTSFUNCTION
DDEA/YB/Z
HHHLActively drive bus high
LHLHActively drive bus low
XLZZDriver disabled
XOPENZZDriver disabled by default
OPENHHLActively drive bus high by default

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH- the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Table 7-2 Receiver Function Table
DIFFERENTIAL INPUTENABLEOUTPUTFUNCTION
VID = VA – VBRER
VTH+ < VIDLHReceive valid bus high
VTH- < VID < VTH+L?Indeterminate bus state
VID < VTH-LLReceive valid bus low
XHZReceiver disabled
XOPENZReceiver disabled by default
Open-circuit busLHFail-safe high output
Short-circuit busLHFail-safe high output
Idle (terminated) busLHFail-safe high output

Table 7-3 shows SLR (slew rate select) pin functionality. SLR has intergated pull-down, so the device remains in higher speed mode until SLR is pulled high which limits the slew rate and puts the device in slower speed mode.

Table 7-3 SLR pin control
Device Functionality w.r.t SLR pin
THVD2410V, THVD2412V SLR = Low or floating: Both transmitter (TX) and receiver (RX) maximum speed is 1 Mbps

SLR = High: Both TX and RX maximum speed is limited to 250 kbps
THVD2450V, THVD2452V SLR = Low or floating: Both transmitter (TX) and receiver (RX) maximum speed is 50 Mbps

SLR = High: Both TX and RX maximum speed is limited to 20 Mbps

Table shows the device behavior in undervoltage scenarios:

Table 7-4 Supply Function Table
VCC VIO Driver Output Receiver Output
> UVVCC(rising) > UVVIO(rising) Determined by DE and D inputs Determined by RE and A-B
< UVVCC(falling) > UVVIO(rising) High impedance High impedance
> UVVCC(rising) < UVVIO(falling) High impedance High impedance
< UVVCC(falling) < UVVIO(falling) High impedance High impedance