SLLSF10 December   2019 TL16C750E

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. 7.1      ESD Ratings
    3. Table 2. Recommended Operating Conditions
    4. Table 3. Thermal Information
    5. Table 4. Electrical Characteristics
    6. Table 5. Timing Requirements
    7. 7.2      Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
        1. 9.4.1.1 IOR Used (MODE = VCC)
        2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
        1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
        2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
    5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Set the desired baud rate
        2. 10.2.2.2 Reset the fifos
        3. 10.2.2.3 Sending data on the bus
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.14 Fractional Divisor

The TL16C750E supports fractional divisors with a fractional resolution of 64 steps. This makes it possible to achieve many baud rates with a single crystal selection.

The following register settings must be configured to use the fractional divider:

  • LCR[7] = 1
  • LCR ≠ 0xBF
  • EFR[4] = 1
  • MCR ≠ 0bx1x0x1xx

    • NOTE

    A 'x' denotes a do not care value of the bit.

To calculate the values necessary to put into the registers, the following functions are needed:

  • TRUNC(X): Truncate X, return just the integer portion of a real number. EX: TRUNC(3.14) = 3
  • ROUND(X): Round X to the nearest integer. EX: ROUND(3.1) = 3 and ROUND(3.6) = 4
  • >>: Bit shift towards the right operation. EX: 0x1000 >> 8 = 0x0010. Or 0b0001 0000 0000 0000 >> 8 = 0b0000 0000 0001 0000
  • &: Bitwise AND function, used to mask bits. EX: 0x1234 & 0x00FF = 0x0034 and 0x8765 & 0xFF00 = 0x8700

Calculating the required divisor is calculated by TL16C750E sllsf10_divisor_equation_raw.gif

Where 'baud divider' is either 8 or 16, depending on the value of DLF[7]. By default, DLF[7] = 0, which corresponds to a baud divider of 16.

Once the required divisor is found, then the register values can be calculated from TL16C750E sllsf10_divisor_equations.gif

Table 12. Baud Rates Using a 24-MHz Crystal and a 16× Baud Divider

DESIRED BAUD RATE DIVISOR USED TO GENERATE 16× CLOCK CLOSEST DIVISOR OBTAINABLE DLH VALUE
(HEX)		 DLL VALUE
(HEX)		 DLF VALUE
(HEX)		 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL (%)
400 3750 3750 0x0E 0xA6 0x00 0
2400 625 625 0x02 0x71 0x00 0
4800 312.5 312 32/64 0x01 0x38 0x20 0
9600 156.25 156 16/64 0x00 0x9C 0x10 0
10000 150 150 0x00 0x96 0x00 0
19200 78.125 78 8/64 0x00 0x4E 0x08 0
25000 60 60 0x00 0x3C 0x00 0
28800 52.0833 52 5/64 0x00 0x34 0x05 0.01
38400 39.0625 39 4/64 0x00 0x27 0x04 0
50000 30 30 0x00 0x1E 0x00 0
57600 26.0417 26 3/64 0x00 0x1A 0x03 0.02
75000 20 20 0x00 0x14 0x00 0
100000 15 15 0x00 0x0F 0x00 0
115200 13.0208 13 1/64 0x00 0x0D 0x01 0.04
153600 9.7656 9 49/64 0x00 0x09 0x31 0
200000 7.5 7 32/64 0x00 0x07 0x20 0
225000 6.6667 6 43/64 0x00 0x06 0x2B 0.08
230400 6.5104 6 33/64 0x00 0x06 0x21 0.08
250000 6 6 0x00 0x06 0x00 0
300000 5 5 0x00 0x05 0x00 0
400000 3.75 3 48/64 0x00 0x03 0x30 0
460800 3.2552 3 16/64 0x00 0x03 0x10 0.16
500000 3 3 0x00 0x03 0x00 0
750000 2 2 0x00 0x02 0x00 0
921600 1.6276 1 40/64 0x00 0x01 0x28 0.16
1000000 1.5 1 32/64 0x00 0x01 0x20 0