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Product details

Parameters

Number of channels (#) 1 FIFOs (bytes) 128 Rx FIFO trigger levels (#) 4 Tx FIFO trigger levels (#) 4 Programmable FIFO trigger levels Yes CPU interface X86, X86 or 68K Baud rate (max) at Vcc = 1.8 V & with 16X sampling (Mbps) 1 Baud rate (max) at Vcc = 2.5 V & with 16X sampling (Mbps) 1.5 Baud rate (max) at Vcc = 3.3 V & with 16X sampling (Mbps) 3 Baud rate (max) at Vcc = 5.0 V & with 16X sampling (Mbps) 6 Operating voltage (V) 1.8, 2.5, 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (C) -40 to 105 open-in-new Find other UARTs

Package | Pins | Size

TQFP (PFB) 48 81 mm² 9 x 9 open-in-new Find other UARTs

Features

  • Supports wide supply voltage range of 1.62 V to 5.5 V
    • 6 Mbps (48-MHz oscillator input clock)
      at 5 V and 3.3 V
    • 3 Mbps (48-MHz oscillator input clock)
      at 5 V and 3.3 V
    • 2 Mbps (32-MHz oscillator input clock)
      at 3.3 V
    • 1.5 Mbps (24-MHz oscillator input clock)
      at 2.5 V
    • 1 Mbps (16-MHz oscillator Input clock)
      at 1.8 V
  • Characterized for operation from –40°C to 105°C
  • 128-byte transmit or receive FIFO
  • 6-bit fractional baud rate divider
  • Software-selectable baud-rate generator
  • Programmable and selectable transmit and Receive FIFO Trigger Levels for DMA, interrupt generation, and software or hardware flow control
  • Software/Hardware flow control
    • Programmable Xon and Xoff characters with optional Xon any character
    • Programmable Auto-RTS and Auto-CTS-modem control functions (CTS, RTS, DSR, DTR, RI, and CD)
  • DMA signaling capability for both received and transmitted data
  • RS-485 mode support
  • Infrared data association (IrDA) capability
  • Programmable sleep mode
  • Programmable serial interface characteristics
    • 5, 6, 7, or 8-bit characters with 1, 1.5, or 2 stop bit generation
    • Even, odd, or no parity bit generation and detection
  • False start bit and line break detection
  • Internal test and loopback capabilities

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Description

The TL16C750E is a single universal asynchronous receiver transmitter (UART) with 128-byte FIFOs, fractional baud rate support, automatic hardware, software flow control and data rates up to 6 Mbps. The device offers enhanced features such as fractional baud rate and a transmission character control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control automatically without intervention from the CPU.

With the FIFO RDY register, the software gets the status of TXRDY or RXRDY, saving extra GPIO usage. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The TL16C750E incorporates the functionality of UART, the UART having its own register set and FIFO.

This version includes the Alternate Function Register (AFR) and this is used to enable some extra functionality beyond the capabilities of the TL16C750 version. One addition is the IrDA mode, which supports Standard IrDA (SIR) mode with baud rates from 2400 to 115.2 kbps. The third addition is support for RS-485 bus drivers or transceivers by providing an output pin (DTRx) per channel, which is timed to keep the RS-485 driver enabled as long as transmit data is pending.

Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C750E device.

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Technical documentation

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Type Title Date
* Datasheet TL16C750E UART with 128-Byte FIFO datasheet May 19, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
199
Description
This EVM provides the user with the ability to evaluate the TL16C750E device and its features. The EVM includes an onboard 3.3-V LDO as well as level translation for processors which operate at a higher voltage rail.
Features
  • Fractional baudrate support
  • 128-byte FIFO depth

Design tools & simulation

SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)

CAD/CAE symbols

Package Pins Download
TQFP (PFB) 48 View options

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