SLVSJD7 February   1997  – July 2025 TLE2021 , TLE2021A , TLE2021M , TLE2022 , TLE2022A , TLE2022AM , TLE2022M , TLE2024 , TLE2024A , TLE2024B , TLE2024BM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Tables
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Thermal Information for TLE2021
    4. 6.4  Thermal Information for TLE2022
    5. 6.5  Thermal Information for TLE2024
    6. 6.6  Electrical Characteristics for TLE2021, VCC = ±15V
    7. 6.7  Electrical Characteristics for TLE2021, VCC = 5V
    8. 6.8  Electrical Characteristics for TLE2022, VCC = ±15V
    9. 6.9  Electrical Characteristics for TLE2022, VCC = 5V
    10. 6.10 Electrical Characteristics for TLE2024, VCC = ±15V
    11. 6.11 Electrical Characteristics for TLE2024, VCC = 5V
    12. 6.12 Typical Characteristics
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Voltage-Follower Applications
      2. 7.1.2 Input Offset Voltage Null
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • P|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 TLE2021: D Package, 8-Pin SOIC, and P Package, 8-Pin PDIP (Top View)
Table 5-1 Pin Functions: TLE2021
PIN TYPE DESCRIPTION
NAME NO.
D (SOIC),
P (PDIP)
–IN 2 Input Inverting input
+IN 3 Input Noninverting input
NC 8 — No connection
OFFSET N1 1 _ External input offset voltage adjustment
OFFSET N2 2 _ External input offset voltage adjustment
OUT 6 Output Output
VCC– 4 Power Negative (lowest) power supply
VCC+ 7 Power Positive (highest) power supply
Figure 5-2 TLE2022: D Package, 8-Pin SOIC and P Package, 8-Pin PDIP (Top View)
Table 5-2 Pin Functions: TLE2022
PIN TYPE DESCRIPTION
NAME NO.
D (SOIC),
P (PDIP)
–IN A 2 Input Inverting input channel A
–IN B 6 Input Inverting input channel B
+IN A 3 Input Noninverting input channel A
+IN B 5 Input Noninverting input channel B
NC — — No connection
OUT A 1 Output Output channel A
OUT B 7 Output Output channel B
VCC– 4 Power Negative supply
VCC+ 8 Power Positive supply
Figure 5-3 TLE2024: N Package, 14-Pin PDIP (Top View)
Figure 5-4 TLE2024: DW Package, 16-Pin (Top View)
Table 5-3 Pin Functions: TLE2024
PIN TYPE DESCRIPTION
NAME NO.
N (PDIP), J (CDIP) DW (SOIC)
–IN A 2 2 Input Inverting input channel A
–IN B 6 6 Input Inverting input channel B
–IN C 9 11 Input Inverting input channel C
–IN D 13 15 Input Inverting input channel D
+IN A 3 3 Input Noninverting input channel A
+IN B 5 5 Input Noninverting input channel B
+IN C 10 12 Input Noninverting input channel C
+IN D 12 14 Input Noninverting input channel D
NC — 8, 9 — No connection
OUT A 1 1 Output Output channel A
OUT B 7 7 Output Output channel B
OUT C 8 10 Output Output channel C
OUT D 14 16 Output Output channel D
VCC– 11 13 Power Negative supply
VCC+ 4 4 Power Positive supply