SLAS510G March   2007  – February 2021 TLV320AIC3104


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Audio Data Serial Interface Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. Right-Justified Mode
        2. Left-Justified Mode
        3. I2S Mode
        4. DSP Mode
        5. TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. Audio Clock Generation
        2. Stereo Audio ADC
          1. Stereo Audio ADC High-Pass Filter
          2. Automatic Gain Control (AGC)
            1. Target Level
            2. Attack Time
            3. Decay Time
            4. Noise Gate Threshold
            5. Maximum PGA Gain Applicable
      4. 10.3.4  Stereo Audio DAC
        1. Digital Audio Processing for Playback
        2. Digital Interpolation Filter
        3. Delta-Sigma Audio DAC
        4. Audio DAC Digital Volume Control
        5. Increasing DAC Dynamic Range
        6. Analog Output Common-Mode Adjustment
        7. Audio DAC Power Control
      5. 10.3.5  Audio Analog Inputs
      6. 10.3.6  Analog Fully Differential Line Output Drivers
      7. 10.3.7  Analog High-Power Output Drivers
      8. 10.3.8  Input Impedance and VCM Control
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Short-Circuit Output Protection
      11. 10.3.11 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. ADC PGA Signal Bypass Path Functionality
        2. Passive Analog Bypass During Power Down
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Interface
        1. I2C Bus Debug in a Glitched System
      2. 10.5.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Typical Connections With Headphone and External Speaker Driver in Portable Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 11.2.2 Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Digital Audio Data Serial Interface

Audio data is transferred between the host processor and the TLV320AIC3104 via the digital audio data serial interface. The audio bus of the TLV320AIC3104 can be configured for left- or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors.

The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling frequency.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used. These cases result in a low-jitter bit clock signal being generated, having frequencies of 32 fS or 64 fS. In the cases of 20-bit and 24-bit data width in master mode, the bit clocks generated in each frame are not all of equal period, due to the device not having a clean 40-fS or 48-fS clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 fS or 48 fS), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3104 further includes programmability to place the DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the digital audio data serial interface is powered down while configured in master mode, the pins associated with the interface are put into a high-impedance state.