SLAS509G April   2006  – July 2021 TLV320AIC3106

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: Audio Data Serial Interface (1)
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 10.3.3.3 Stereo Audio DAC
          1. 10.3.3.3.1 Digital Audio Processing for Playback
          2. 10.3.3.3.2 Digital Interpolation Filter
          3. 10.3.3.3.3 Delta-Sigma Audio DAC
          4. 10.3.3.3.4 Audio DAC Digital Volume Control
          5. 10.3.3.3.5 Increasing DAC Dynamic Range
          6. 10.3.3.3.6 Analog Output Common-Mode Adjustment
          7. 10.3.3.3.7 Audio DAC Power Control
      4. 10.3.4  Audio Analog Inputs
      5. 10.3.5  Analog Fully Differential Line Output Drivers
      6. 10.3.6  Analog High Power Output Drivers
      7. 10.3.7  Input Impedance and VCM Control
      8. 10.3.8  General-Purpose I/O
      9. 10.3.9  Digital Microphone Connectivity
      10. 10.3.10 Micbias Generation
      11. 10.3.11 Short Circuit Output Protection
      12. 10.3.12 Jack/Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 Analog Input Bypass Path Functionality
        2. 10.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 10.4.1.3 Passive Analog Bypass During Powerdown
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 Digital Control Serial Interface
        1. 10.5.1.1 SPI Control Mode
          1. 10.5.1.1.1 SPI Communication Protocol
          2. 10.5.1.1.2 Limitation on Register Writing
          3. 10.5.1.1.3 Continuous Read / Write Operation
        2. 10.5.1.2 I2C Control Interface
          1. 10.5.1.2.1 I2C BUS Debug in a Glitched System
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.6 Register Maps

The register map of the TLV320AIC3106 actually consists of multiple pages of registers, with each page containing 128 registers. The register at address zero on each page is used as a page-control register, and writing to this register determines the active page for the device. All subsequent read/write operations will access the page that is active at the time, unless a register write is performed to change the active page. Only two pages of registers are implemented in this product, with the active page defaulting to page 0 upon device reset.

For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page 1. After this write, it is recommended the user also read back the page control register, to safely ensure the change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence 0x00 to register 0, the page control register, to change the active page back to page 0. After a recommended read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0 registers again.

The control registers for the TLV320AIC3106 are described in detail below. All registers are 8 bit in width, with D7 referring to the most significant bit of each register, and D0 referring to the least significant bit.

Table 10-8 Page 0 / Register 0: Page Select Register
BIT(1)READ/
WRITE		RESET
VALUE		DESCRIPTION
D7–D1X0000 000Reserved, write only zeros to these register bits
D0R/W0Page Select Bit
Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a one to this bit sets Page-1 as the active page for following register accesses. It is recommended that the user read this register bit back after each write, to ensure that the proper page is being accessed for future register read/writes.
(1) When resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to the registers instead of using software reset.
Table 10-9 Page 0 / Register 1: Software Reset Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7W0Software Reset Bit
0 : Don’t Care
1 : Self clearing software reset
D6–D0W000 0000Reserved; don’t write
Table 10-10 Page 0 / Register 2: Codec Sample Rate Select Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D4R/W0000ADC Sample Rate Select
0000: ADC fS = fS(ref)/1
0001: ADC fS = fS(ref)/1.5
0010: ADC fS = fS(ref)/2
0011: ADC fS = fS(ref)/2.5
0100: ADC fS = fS(ref)/3
0101: ADC fS = fS(ref)/3.5
0110: ADC fS = fS(ref)/4
0111: ADC fS = fS(ref)/4.5
1000: ADC fS = fS(ref)/5
1001: ADC fS = fS(ref)/5.5
1010: ADC fS = fS(ref)/6
1011–1111: Reserved, do not write these sequences.
D3–D0R/W0000DAC Sample Rate Select
0000 : DAC fS = fS(ref)/1
0001 : DAC fS = fS(ref)/1.5
0010 : DAC fS = fS(ref)/2
0011 : DAC fS = fS(ref)/2.5
0100 : DAC fS = fS(ref)/3
0101 : DAC fS = fS(ref)/3.5
0110 : DAC fS = fS(ref)/4
0111 : DAC fS = fS(ref)/4.5
1000 : DAC fS = fS(ref)/5
1001: DAC fS = fS(ref)/5.5
1010: DAC fS = fS(ref) / 6
1011–1111 : Reserved, do not write these sequences.
Table 10-11 Page 0 / Register 3: PLL Programming Register A
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0PLL Control Bit
0: PLL is disabled
1: PLL is enabled
D6–D3R/W0010PLL Q Value
0000: Q = 16
0001 : Q = 17
0010 : Q = 2
0011 : Q = 3
0100 : Q = 4
…
1110: Q = 14
1111: Q = 15
D2–D0R/W000PLL P Value
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
Table 10-12 Page 0 / Register 4: PLL Programming Register B
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D2R/W0000 01PLL J Value
0000 00: Reserved, do not write this sequence
0000 01: J = 1
0000 10: J = 2
0000 11: J = 3
…
1111 10: J = 62
1111 11: J = 63
D1–D0R/W00Reserved, write only zeros to these bits
Table 10-13 Page 0 / Register 5: PLL Programming Register C(1)
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D0R/W0000 0000PLL D value – Eight most significant bits of a 14-bit unsigned integer valid values for D are from zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written into these registers that would result in a D value outside the valid range.
(1) Note that whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or LSB of the value changes, both registers should be written.
Table 10-14 Page 0 / Register 6: PLL Programming Register D
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D2R/W0000 0000PLL D value – Six least significant bits of a 14-bit unsigned integer valid values for D are from zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be written into these registers that would result in a D value outside the valid range.
D1–D0R00Reserved, write only zeros to these bits.
Table 10-15 Page 0 / Register 7: Codec Datapath Setup Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0fS(ref) setting
This register setting controls timers related to the AGC time constants.
0: fS(ref) = 48 kHz
1: fS(ref) = 44.1 kHz
D6R/W0ADC Dual rate control
0: ADC dual rate mode is disabled
1: ADC dual rate mode is enabled
Note: ADC Dual Rate Mode must match DAC Dual Rate Mode
D5R/W0DAC Dual Rate Control
0: DAC dual rate mode is disabled
1: DAC dual rate mode is enabled
D4–D3R/W00Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D2–D1R/W00Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
D0R/W0Reserved. Only write zero to this register.
Table 10-16 Page 0 / Register 8: Audio Serial Data Interface Control Register A
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0Bit Clock Directional Control
0: BCLK (or GPIO2 if programmed as BCLK) is an input (slave mode)
1: BCLK (or GPIO2 if programmed as BCLK) is an output (master mode)
D6R/W0Word Clock Directional Control
0: WCLK (or GPIO1 if programmed as WCLK) is an input (slave mode)
1: WCLK (or GPIO1 if programmed as WCLK) is an output (master mode)
D5R/W0Serial Output Data Driver (DOUT) 3-State Control
0: Do not place DOUT in high-impedance state when valid data is not being sent
1: Place DOUT in high-impedance state when valid data is not being sent
D4R/W0Bit/ Word Clock Drive Control
0:BCLK (or GPIO2 if programmed as BCLK) / WCLK (or GPIO1 if programmed as WCLK) will not continue to be transmitted when running in master mode if codec is powered down
1:BCLK (or GPIO2 if programmed as BCLK) / WCLK (or GPIO1 if programmed as WCLK) continues to be transmitted when running in master mode, even if codec is powered down
D3R/W0Reserved. Don’t write to this register bit.
D2R/W03-D Effect Control
0: Disable 3-D digital effect processing
1: Enable 3-D digital effect processing
D1–D0R/W00Digital Microphone Functionality Control
00: Digital microphone support is disabled
01: Digital microphone support is enabled with an oversampling rate of 128
10: Digital microphone support is enabled with an oversampling rate of 64
11: Digital microphone support is enabled with an oversampling rate of 32
Table 10-17 Page 0 / Register 9: Audio Serial Data Interface Control Register B
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00Audio Serial Data Interface Transfer Mode
00: Serial data bus uses I2S mode
01: Serial data bus uses DSP mode
10: Serial data bus uses right-justified mode
11: Serial data bus uses left-justified mode
D5–D4R/W00Audio Serial Data Word Length Control
00: Audio data word length = 16 bits
01: Audio data word length = 20 bits
10: Audio data word length = 24 bits
11: Audio data word length = 32 bits
D3R/W0Bit Clock Rate Control
This register only has effect when bit clock is programmed as an output
0: Continuous-transfer mode used to determine master mode bit clock rate
1: 256-clock transfer mode used, resulting in 256 bit clocks per frame
D2R/W0DAC Re-Sync
0: Don’t Care
1:Re-sync stereo DAC with codec interface if the group delay changes by more than ±DACFS/4.
D1R/W0ADC Re-Sync
0: Don’t Care
1:Re-sync stereo ADC with codec interface if the group delay changes by more than ±ADCFS/4.
D0R/WRe-Sync Mute Behavior
0: Re-sync is done without soft-muting the channel. (ADC/DAC)
1: Re-sync is done by internally soft-muting the channel. (ADC/DAC)
Table 10-18 Page 0 / Register 10: Audio Serial Data Interface Control Register C
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D0R/W0000 0000Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling the offset from beginning of the frame where valid data begins. The offset is measured from the rising edge of word clock when in DSP mode.
0000 0000: Data offset = 0 bit clocks
0000 0001: Data offset = 1 bit clock
0000 0010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode the maximum offset is 17 for I2S/LJF/RJF modes and 16 for DSP mode. In 256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for DSP modes.
1111 1110: Data offset = 254 bit clocks
1111 1111: Data offset = 255 bit clocks
Table 10-19 Page 0 / Register 11: Audio Codec Overflow Flag Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R0Left ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D6R0Right ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D5R0Left DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D4R0Right DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D3–D0R/W0001PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
Table 10-20 Page 0 / Register 12: Audio Codec Digital Filter Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00Left ADC Highpass Filter Control
00: Left ADC highpass filter disabled
01: Left ADC highpass filter –3-dB frequency = 0.0045 × ADC fS
10: Left ADC highpass filter –3-dB frequency = 0.0125 × ADC fS
11: Left ADC highpass filter –3-dB frequency = 0.025 × ADC fS
D5–D4R/W00Right ADC Highpass Filter Control
00: Right ADC highpass filter disabled
01: Right ADC highpass filter –3-dB frequency = 0.0045 × ADC fS
10: Right ADC highpass filter –3-dB frequency = 0.0125 × ADC fS
11: Right ADC highpass filter –3-dB frequency = 0.025 × ADC fS
D3R/W0Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2R/W0Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
D1R/W0Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
D0R/W0Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
Table 10-21 Page 0 / Register 13: Headset / Button Press Detection Register A
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
D6–D5R00Headset Type Detection Results
00: No headset detected
01: Headset without microphone detected
10: Ignore (reserved)
11: Headset with microphone detected
D4–D2R/W000Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16 ms (sampled with 2-ms clock)
001: Debounce = 32 ms (sampled with 4-ms clock)
010: Debounce = 64 ms (sampled with 8-ms clock)
011: Debounce = 128 ms (sampled with 16-ms clock)
100: Debounce = 256 ms (sampled with 32-ms clock)
101: Debounce = 512 ms (sampled with 64-ms clock)
110: Reserved, do not write this bit sequence to these register bits.
111: Reserved, do not write this bit sequence to these register bits.
D1–D0R/W00Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0msec
01: Debounce = 8 ms (sampled with 1-ms clock)
10: Debounce = 16 ms (sampled with 2-ms clock)
11: Debounce = 32 ms (sampled with 4-ms clock)
Table 10-22 Page 0 / Register 14: Headset / Button Press Detection Register B
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6(1)R/W0Stereo Output Driver Configuration A
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo fully differential output configuration is not being used
1: A stereo fully differential output configuration is being used
D5R0Button Press Detection Flag
This register is a sticky bit, and will stay set to 1 after a button press has been detected, until the register is read. Upon reading this register, the bit is reset to zero.
0: A button press has not been detected
1: A button press has been detected
D4R0Headset Detection Flag
0: A headset has not been detected
1: A headset has been detected
D3(1)R/W0Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudodifferential output configuration is not being used
1: A stereo pseudodifferential output configuration is being used
D2–D0R000Reserved. Write only zeros to these bits.
(1) Do not set D6 and D3 to 1 simultaneously
Table 10-23 Page 0 / Register 15: Left ADC PGA Gain Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W1Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
D6–D0R/W000 0000Left ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB 0000010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
Table 10-24 Page 0 / Register 16: Right ADC PGA Gain Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W1Right ADC PGA Mute
0: The right ADC PGA is not muted
1: The right ADC PGA is muted
D6–D0R/W000 0000Right ADC PGA Gain Setting
000 0000: Gain = 0 dB
000 0001: Gain = 0.5 dB
000 0010: Gain = 1 dB
…
111 0110: Gain = 59 dB
111 0111: Gain = 59.5 dB
111 1000: Gain = 59.5 dB
…
111 1111: Gain = 59.5 dB
Table 10-25 Page 0 / Register 17: MIC3L/R to Left ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D4R/W1111MIC3L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the left ADC PGA
D3–D0R/W1111MIC3R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to the left ADC PGA
Table 10-26 Page 0 / Register 18: MIC3L/R to Right ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D4R/W1111MIC3L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the right ADC PGA
D3–D0R/W1111MIC3R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to right ADC PGA
Table 10-27 Page 0 / Register 19: LINE1L to Left ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
D6–D3R/W1111LINE1L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the left ADC PGA
D2R/W0Left ADC Channel Power Control
0: Left ADC channel is powered down
1: Left ADC channel is powered up
D1–D0R/W00Left ADC PGA Soft-Stepping Control
00: Left ADC PGA soft-stepping at once per fS
01: Left ADC PGA soft-stepping at once per two fS
10–11: Left ADC PGA soft-stepping is disabled
Table 10-28 Page 0 / Register 20: LINE2L to Left(1) ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0LINE2L Single-Ended vs Fully Differential Control
If LINE2L is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
0: LINE2L is configured in single-ended mode
1: LINE2L is configured in fully differential mode
D6–D3R/W1111LINE2L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2L to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE2L is not connected to the left ADC PGA
D2R/W0Left ADC Channel Weak Common-Mode Bias Control
0:Left ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1:Left ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1–D0R00Reserved. Write only zeros to these register bits
(1) LINE1R SEvsFD control is available for both left and right channels. However this setting must be same for both the channels.
Table 10-29 Page 0 / Register 21: LINE1R to Left ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3R/W1111LINE1R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the left ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1R is not connected to the left ADC PGA
D2–D0R000Reserved. Write only zeros to these register bits.
Table 10-30 Page 0 / Register 22: LINE1R to Right ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3R/W1111LINE1R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1R is not connected to the right ADC PGA
D2R/W0Right ADC Channel Power Control
0: Right ADC channel is powered down
1: Right ADC channel is powered up
D1–D0R/W00Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per fS
01: Right ADC PGA soft-stepping at once per two fS
10–11: Right ADC PGA soft-stepping is disabled
Table 10-31 Page 0 / Register 23: LINE2R to Right ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0LINE2R Single-Ended vs Fully Differential Control
If LINE2R is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
0: LINE2R is configured in single-ended mode
1: LINE2R is configured in fully differential mode
D6–D3R/W1111LINE2R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2R to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE2R is not connected to the right ADC PGA
D2R/W0Right ADC Channel Weak Common-Mode Bias Control
0:Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
1:Right ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1–D0R00Reserved. Write only zeros to these register bits
Table 10-32 Page 0 / Register 24: LINE1L to Right ADC Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
D6–D3R/W1111LINE1L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the right ADC PGA mix
0000: Input level control gain = 0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the right ADC PGA
D2–D0R000Reserved. Write only zeros to these register bits.
Table 10-33 Page 0 / Register 25: MICBIAS Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0V
10: MICBIAS output is powered to 2.5V
11: MICBIAS output is connected to AVDD
D5–D4R/W00Digital Microphone Control
00: If Digital MIC is enabled, both Left and Right Digital MICs are available
01: If Digital MIC is enabled, Left Digital MIC and Right ADC are available
10: If Digital MIC is enabled, Left ADC and Right Digital MIC are available
11: Reserved. Don’t write to this sequence.
D3R0Reserved. Don’t write to this register bit.
D2–D0RXXXReserved. Write only zeros to these register bits.
Table 10-34 Page 0 / Register 26: Left AGC Control Register A
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0Left AGC Enable
0: Left AGC is disabled
1: Left AGC is enabled
D6–D4R/W000Left AGC Target Level
000: Left AGC target level = –5.5 dB
001: Left AGC target level = –8 dB
010: Left AGC target level = –10 dB
011: Left AGC target level = –12 dB
100: Left AGC target level = –14 dB
101: Left AGC target level = –17 dB
110: Left AGC target level = –20 dB
111: Left AGC target level = –24 dB
D3–D2R/W00Left AGC Attack Time
These time constants(1) will not be accurate when double rate audio mode is enabled.
00: Left AGC attack time = 8 ms
01: Left AGC attack time = 11 ms
10: Left AGC attack time = 16 ms
11: Left AGC attack time = 20 ms
D1–D0R/W00Left AGC Decay Time
These time constants(1) will not be accurate when double rate audio mode is enabled.
00: Left AGC decay time = 100 ms
01: Left AGC decay time = 200 ms
10: Left AGC decay time = 400 ms
11: Left AGC decay time = 500 ms
(1) Time constants are valid when DRA is not enabled. The values would change if DRA is enabled.
Table 10-35 Page 0 / Register 27: Left AGC Control Register B
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D1R/W1111 111Left AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
D0R/W0Reserved. Write only zero to this register bit.
Table 10-36 Page 0 / Register 28: Left AGC Control Register C
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00Noise Gate Hysteresis Level Control
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled
D5–D1R/W00 000Left AGC Noise Threshold Control
00 000: Left AGC Noise/Silence Detection disabled
00 001: Left AGC noise threshold = –30 dB
00 010: Left AGC noise threshold = –32 dB
00 011: Left AGC noise threshold = –34 dB
…
11 101: Left AGC noise threshold = –86 dB
11 110: Left AGC noise threshold = –88 dB
11 111: Left AGC noise threshold = –90 dB
D0R/W0Left AGC Clip Stepping Control
0: Left AGC clip stepping disabled
1: Left AGC clip stepping enabled
Table 10-37 Page 0 / Register 29: Right AGC Control Register A
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0Right AGC Enable
0: Right AGC is disabled
1: Right AGC is enabled
D6–D4R/W000Right AGC Target Level
000: Right AGC target level = –5.5 dB
001: Right AGC target level = –8 dB
010: Right AGC target level = –10 dB
011: Right AGC target level = –12 dB
100: Right AGC target level = –14 dB
101: Right AGC target level = –17 dB
110: Right AGC target level = –20 dB
111: Right AGC target level = –24 dB
D3–D2R/W00Right AGC Attack Time
These time constants will not be accurate when double rate audio mode is enabled.
00: Right AGC attack time = 8 ms
01: Right AGC attack time = 11 ms
10: Right AGC attack time = 16 ms
11: Right AGC attack time = 20 ms
D1–D0R/W00Right AGC Decay Time
These time constants will not be accurate when double rate audio mode is enabled.
00: Right AGC decay time = 100 ms
01: Right AGC decay time = 200 ms
10: Right AGC decay time = 400 ms
11: Right AGC decay time = 500 ms
Table 10-38 Page 0 / Register 30: Right AGC Control Register B
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D1R/W1111 111Right AGC Maximum Gain Allowed
0000 000: Maximum gain = 0 dB
0000 001: Maximum gain = 0.5 dB
0000 010: Maximum gain = 1 dB
…
1110 110: Maximum gain = 59 dB
1110 111–1111 111: Maximum gain = 59.5 dB
D0R/W0Reserved. Write only zero to this register bit.
Table 10-39 Page 0 / Register 31: Right AGC Control Register C
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00Noise Gate Hysteresis Level Control
00: Hysteresis = 1 dB
01: Hysteresis = 2 dB
10: Hysteresis = 3 dB
11: Hysteresis is disabled
D5–D1R/W00 000Right AGC Noise Threshold Control
00 000: Right AGC Noise/Silence Detection disabled
00 001: Right AGC noise threshold = –30 dB
00 010: Right AGC noise threshold = –32 dB
00 011: Right AGC noise threshold = –34 dB
…
11 101: Right AGC noise threshold = –86 dB
11 110: Right AGC noise threshold = –88 dB
11 111: Right AGC noise threshold = –90 dB
D0R/W0Right AGC Clip Stepping Control
0: Right AGC clip stepping disabled
1: Right AGC clip stepping enabled
Table 10-40 Page 0 / Register 32: Left AGC Gain Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D0R0000 0000Left Channel Gain Applied by AGC Algorithm
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
Table 10-41 Page 0 / Register 33: Right AGC Gain Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D0R0000 0000Right Channel Gain Applied by AGC Algorithm
1110 1000: Gain = –12 dB
1110 1001: Gain = –11.5 dB
1110 1010: Gain = –11 dB
…
0000 0000: Gain = 0 dB
0000 0001: Gain = 0.5 dB
…
0111 0110: Gain = 59 dB
0111 0111: Gain = 59.5 dB
Table 10-42 Page 0 / Register 34: Left AGC Noise Gate Debounce Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D3R/W0000 0Left AGC Noise Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64×1 = 64ms
0100 1: Debounce = 64×2 = 128ms
0101 0: Debounce = 64×3 = 192ms
…
1111 0: Debounce = 64×23 = 1472ms
1111 1: Debounce = 64×24 = 1536ms
D2–D0R/W000Left AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled
Table 10-43 Page 0 / Register 35: Right AGC Noise Gate Debounce Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D3R/W0000 0Right AGC Noise Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
0000 0: Debounce = 0 ms
0000 1: Debounce = 0.5 ms
0001 0: Debounce = 1 ms
0001 1: Debounce = 2 ms
0010 0: Debounce = 4 ms
0010 1: Debounce = 8 ms
0011 0: Debounce = 16 ms
0011 1: Debounce = 32 ms
0100 0: Debounce = 64 × 1 = 64 ms
0100 1: Debounce = 64 × 2 = 128 ms
0101 0: Debounce = 64 × 3 = 192 ms
…
1111 0: Debounce = 64 × 23 = 1472 ms
1111 1: Debounce = 64 × 24 = 1536 ms
D2–D0R/W000Right AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0 ms
001: Debounce = 0.5 ms
010: Debounce = 1 ms
011: Debounce = 2 ms
100: Debounce = 4 ms
101: Debounce = 8 ms
110: Debounce = 16 ms
111: Debounce = 32 ms
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.
Table 10-44 Page 0 / Register 36: ADC Flag Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R0Left ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D6R0Left ADC Power Status
0: Left ADC is in a power down state
1: Left ADC is in a power up state
D5R0Left AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D4R0Left AGC Saturation Flag
0: Left AGC is not saturated
1: Left AGC gain applied = maximum allowed gain for left AGC
D3R0Right ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D2R0Right ADC Power Status
0: Right ADC is in a power down state
1: Right ADC is in a power up state
D1R0Right AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
D0R0Right AGC Saturation Flag
0: Right AGC is not saturated
1: Right AGC gain applied = maximum allowed gain for right AGC
Table 10-45 Page 0 / Register 37: AC Power and Output Driver Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W0Left DAC Power Control
0: Left DAC not powered up
1: Left DAC is powered up
D6R/W0Right DAC Power Control
0: Right DAC not powered up
1: Right DAC is powered up
D5–D4R/W00HPLCOM Output Driver Configuration Control
00: HPLCOM configured as differential of HPLOUT
01: HPLCOM configured as constant VCM output
10: HPLCOM configured as independent single-ended output
11: Reserved. Do not write this sequence to these register bits.
D3–D0R000Reserved. Write only zeros to these register bits.
Table 10-46 Page 0 / Register 38: High-Power Output Driver Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R00Reserved. Write only zeros to these register bits.
D5–D3R/W000HPRCOM Output Driver Configuration Control
000: HPRCOM configured as differential of HPROUT
001: HPRCOM configured as constant VCM output
010: HPRCOM configured as independent single-ended output
011: HPRCOM configured as differential of HPLCOM
100: HPRCOM configured as external feedback with HPLCOM as constant VCM output
101–111: Reserved. Do not write these sequences to these register bits.
D2R/W0Short Circuit Protection Control
0: Short circuit protection on all high power output drivers is disabled
1: Short circuit protection on all high power output drivers is enabled
D1R/W0Short-Circuit Protection Mode Control
0: If short circuit protection enabled, it will limit the maximum current to the load
1: If short circuit protection enabled, it will power down the output driver automatically when a short is detected
D0R0Reserved. Write only zero to this register bit.
Table 10-47 Page 0 / Register 39: Reserved Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D0R0000 0000Reserved. Do not write to this register.
Table 10-48 Page 0 / Register 40: High Power Output Stage Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00Output Common-Mode Voltage Control
00: Output common-mode voltage = 1.35 V
01: Output common-mode voltage = 1.5 V
10: Output common-mode voltage = 1.65 V
11: Output common-mode voltage = 1.8 V
D5–D4R/W00LINE2L Bypass Path Control
00: LINE2L bypass is disabled
01: LINE2L bypass uses LINE2LP single-ended
10: LINE2L bypass uses LINE2LM single-ended
11: LINE2L bypass uses LINE2LP/M differentially
D3–D2R/W00LINE2R Bypass Path Control
00: LINE2R bypass is disabled
01: LINE2R bypass uses LINE2RP single-ended
10: LINE2R bypass uses LINE2RM single-ended
11: LINE2R bypass uses LINE2RP/M differentially
D1–D0R/W00Output Volume Control Soft-Stepping
00: Output soft-stepping = one step per fS
01: Output soft-stepping = one step per 2 fS
10: Output soft-stepping disabled
11: Reserved. Do not write this sequence to these register bits.
Table 10-49 Page 0 / Register 41: DAC Output Switching Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D6R/W00Left DAC Output Switching Control
00: Left DAC output selects DAC_L1 path
01: Left DAC output selects DAC_L3 path to left line output driver
10: Left DAC output selects DAC_L2 path to left high power output drivers
11: Reserved. Do not write this sequence to these register bits.
D5–D4R/W00Right DAC Output Switching Control
00: Right DAC output selects DAC_R1 path
01: Right DAC output selects DAC_R3 path to right line output driver
10: Right DAC output selects DAC_R2 path to right high power output drivers
11: Reserved. Do not write this sequence to these register bits.
D3–D2R/W00Reserved. Write only zeros to these bits.
D1–D0R/W00DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
Table 10-50 Page 0 / Register 42: Output Driver Pop Reduction Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7–D4R/W0000Output Driver Power-On Delay Control
0000: Driver power-on time = 0 μs
0001: Driver power-on time = 10 μs
0010: Driver power-on time = 100 μs
0011: Driver power-on time = 1 ms
0100: Driver power-on time = 10 ms
0101: Driver power-on time = 50 ms
0110: Driver power-on time = 100 ms
0111: Driver power-on time = 200 ms
1000: Driver power-on time = 400 ms
1001: Driver power-on time = 800 ms
1010: Driver power-on time = 2 s
1011: Driver power-on time = 4 s
1100–1111: Reserved. Do not write these sequences to these register bits.
D3–D2R/W00Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 1 ms
10: Driver ramp-up step time = 2 ms
11: Driver ramp-up step time = 4 ms
D1R/W0Weak Output Common-mode Voltage Control
0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply
1: Weakly driven output common-mode voltage is generated from bandgap reference
D0R/W0Reserved. Write only zero to this register bit.
Table 10-51 Page 0 / Register 43: Left DAC Digital Volume Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W1Left DAC Digital Mute
0: The left DAC channel is not muted
1: The left DAC channel is muted
D6–D0R/W000 0000Left DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB
Table 10-52 Page 0 / Register 44: Right DAC Digital Volume Control Register
BITREAD/
WRITE		RESET
VALUE		DESCRIPTION
D7R/W1Right DAC Digital Mute
0: The right DAC channel is not muted
1: The right DAC channel is muted
D6–D0R/W000 0000Right DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = –0.5 dB
000 0010: Gain = –1 dB
…
111 1101: Gain = –62.5 dB
111 1110: Gain = –63 dB
111 1111: Gain = –63.5 dB