SNOSDA2E august   2020  – july 2023 TLV3604 , TLV3605 , TLV3607

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Configurations: TLV3604 and TLV3605
    2. 5.1 Pin Configuration: TLV3607
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VCCI = VCCO = 2.5 V to 5 V)
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Rail-to-Rail Inputs
      2. 7.4.2 LVDS Output
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Comparator Inputs
      2. 8.1.2 Capacitive Loads
      3. 8.1.3 Latch Functionality
      4. 8.1.4 Adjustable Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Non-Inverting Comparator With Hysteresis
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Optical Receiver
      3. 8.2.3 Logic Clock Source to LVDS Transceiver
      4. 8.2.4 External Trigger Function for Oscilloscopes
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

First, create an equation for VT that covers both output voltages when the output is high or low.
Equation 1. VINN_LOW = VREF - (VREF - VOL) x R1 / (R1 + R2)
Equation 2. VINN_HI = VREF - (VREF - VOH) x R1 / (R1 + R2)
The hysteresis voltage in this network is equal to the difference in the two threshold voltage equations.
Equation 3. VHYS = VINN_HI - VINN_LOW
Equation 4. After simplifying: VHYS = (VOH - VOL) x R1 / (R1 + R2)

Since input bias is typically 1 µA, it is best to choose a value for R1 and then solve for the required R2 to provided the needed amount of hysteresis. In this example, a value of 500 Ω was selected to minimize the impact of input bias current on circuit offset voltage. Solving for R2 provides the equation below. Note that VOD is 350 mV from the EC Table.

Equation 5. R2 = R1 x (VOD - VHYS) / VHYS

VREF can now be solved for using the equation for VINN_LOW or VINN_HI. IN this example, VINN_HI was chosen.

Equation 6. VREF = (VINN_HI - k x VOH) / (1 - k) where k = R1 / (R1 + R2)

The external hysteresis design is now complete with R1 = 500 Ω, R2 = 8.25 kΩ, VREF = 2.8 V.