SLVSI74A July   2025  – November 2025 TLV61290

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 I2C Interface Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting
      2. 7.3.2 Switching frequency and Spread Spectrum Function
    4. 7.4 Device Functional Modes
      1. 7.4.1  Enable and Start-up
      2. 7.4.2  Operation Mode Setting
      3. 7.4.3  Bypass Mode
      4. 7.4.4  Boost Control Operation
      5. 7.4.5  Auto PFM Mode
      6. 7.4.6  Forced PWM Mode
      7. 7.4.7  Ultrasonic Mode
      8. 7.4.8  Output Discharge
      9. 7.4.9  Undervoltage Lockout
      10. 7.4.10 Current Limit Operation
      11. 7.4.11 Output Short-to-Ground Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Power-Good Indication Status
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 DeviceID Register
      2. 7.6.2 CONFIG Register
      3. 7.6.3 VOUTFLOORSET Register
      4. 7.6.4 ILIMBSTSET Register
      5. 7.6.5 VOUTROOFSET Register
      6. 7.6.6 STATUS Register
      7. 7.6.7 ILIMPTSET Register
      8. 7.6.8 BSTLOOP Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 TLV61290 with 2.5V-4.35V VIN, 3.4V VOUT, 4A Output Current
        1. 8.2.1.1 Design Requirement
        2. 8.2.1.2 Detailed Design Parameters
          1. 8.2.1.2.1 Inductor Selection
          2. 8.2.1.2.2 Output Capacitor
          3. 8.2.1.2.3 Input Capacitor
          4. 8.2.1.2.4 Checking Loop Stability
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Information
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1.     79

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.1.2.2 Output Capacitor

For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors that do not fit close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly recommended. To get an estimate of the recommended minimum output capacitance, use Equation 9.

Equation 9. CMIN=IOUT×VOUT-VINf×∆V×VOUT

where f is the switching frequency and ΔV is the maximum allowed output ripple.

The total ripple will be larger due to the ESR and ESL of the output capacitor. Calculate this additional component of the ripple using:

Equation 10. ∆VOUTESR=ESR×IOUT1-D+∆IL2
Equation 11. ∆VOUTESL=ESL×IOUT1-D+∆IL2-IOUT×1tSW(RISE)
Equation 12. ∆VOUTESL=ESL×IOUT1-D-∆IL2-IOUT×1tSW(FALL)

where

  • IOUT = output current of the application
  • D = duty cycle
  • ΔIL = inductor ripple current
  • tSW(RISE) = switch node rise time
  • tSW(FALL) = switch node fall time
  • ESR = equivalent series resistance of the used output capacitor
  • ESL = equivalent series inductance of the used output capacitor

Use an MLCC capacitor with twice the value of the calculated minimum because of the DC bias effects. This capacitor is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause lower output voltage ripple as well as lower output voltage drop during load transients.

For most of the application cases, 2pcs 22µF X5R 10V (0603) MLCC capacitors is recommended to use.

In applications featuring high (pulsed) load currents (for example: ≥ 3.4V / 4A), it is recommended to run the converter with a reasonable amount of effective output capacitance and low-ESL device, for instance 3pcs 22µF X5R 10V (0603) MLCC capacitors.

DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the effective capacitance of the device. Therefore the right capacitor value has to be chosen very carefully. Package size and voltage rating in combination with material are responsible for differences between the rated capacitor value and effective capacitance of the capacitor. For instance, a 22µF X5R 6.3V (0603) MLCC capacitor typically shows an effective capacitance of less than 10µF (under 3.4V DC bias and 20mV AC bias condition).

For RF Power Amplifier applications, the output capacitor loading is combined between the DC/DC converter and the RF Power Amplifier + PA input capacitors.

High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore the regulation circuit has no voltage drop to react on. Nevertheless, for accurate output voltage regulation even with low ESR, the regulation loop switches to a pure comparator regulation scheme.