SBOS943E February   2019  – August 2021 TLV9101 , TLV9102 , TLV9104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  EMI Rejection
      2. 7.3.2  Phase Reversal Protection
      3. 7.3.3  Thermal Protection
      4. 7.3.4  Capacitive Load and Stability
      5. 7.3.5  Common-Mode Voltage Range
      6. 7.3.6  Electrical Overstress
      7. 7.3.7  Overload Recovery
      8. 7.3.8  Typical Specifications and Distributions
      9. 7.3.9  Packages With an Exposed Thermal Pad
      10. 7.3.10 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High Voltage Precision Comparator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics

For VS = (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VO UT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– ±0.3 ±1.5 mV
TA = –40°C to 125°C ±1.75
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.6 µV/℃
PSRR Input offset voltage versus power supply VCM = V– TA = –40°C to 125°C ±0.1 ±0.7 µV/V
Channel separation f = 0 Hz 5 µV/V
INPUT BIAS CURRENT
IB Input bias current ±10 pA
IOS Input offset current ±5 pA
NOISE
EN Input voltage noise f = 0.1 Hz to 10 Hz   6 µVPP
  1   µVRMS
eN Input voltage noise density f = 1 kHz 30   nV/√Hz
f = 10 kHz   28  
iN Input current noise f = 1 kHz   2   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VS = 16 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) TA = –40°C to 125°C 90 110 dB
VS = 4 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) 75 95
VS = 2.7 – 16 V, (V+) – 1 V < VCM < (V+) + 0.1 V (Aux input pair) 80
(V+) – 2 V < VCM < (V+) – 1 V See Offset Voltage (Transition Region) in the Typical Characteristics section
INPUT CAPACITANCE
ZID Differential 100 || 3 MΩ || pF
ZICM Common-mode 6 || 1 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 16 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –  0.1 V		 TA = –40°C to 125°C 115 135 dB
VS = 4 V, VCM = V–
(V–) + 0.1 V < VO < (V+) –  0.1 V		 104 125 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1.1 MHz
SR Slew rate VS = 16 V, G = +1, CL = 20 pF 4.5 V/µs
tS Settling time To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF 4 µs
To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF 2
To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF 5
To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF 3
Phase margin G = +1, RL = 10 kΩ, CL = 20 pF 60 °
Overload recovery time VIN  × gain > VS 600 ns
THD+N Total harmonic distortion + noise VS = 16 V, VO = 1 VRMS, G = -1, f = 1 kHz 0.0028%
OUTPUT
  Voltage output swing from rail Positive and negative rail headroom VS = 16 V, RL = no load   3 mV
VS = 16 V, RL = 10 kΩ   45 60
VS = 16 V, RL = 2 kΩ   200 300
VS = 2.7 V, RL = no load   1
VS = 2.7 V, RL = 10 kΩ   5 20
VS = 2.7 V, RL = 2 kΩ   25 50
ISC Short-circuit current ±80 mA
CLOAD Capacitive load drive See Small-Signal Overshoot vs Capacitive Load in the Typical Characteristics section
ZO Open-loop output impedance f = 1 MHz, IO = 0 A 600 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 115 150 µA
TA = –40°C to 125°C 160
SHUTDOWN
IQSD Quiescent current per amplifier VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V+ 20 30 µA
ZSHDN Output impedance during shutdown VS = 2.7 V to 16 V, amplifier disabled, SHDN = V+ 10 || 12 GΩ || pF
VIH Logic high threshold voltage (amplifier disabled) For valid input high, the SHDN pin voltage should be greater than the maximum threshold but less than or equal to V+ (V–) + 0.8 (V–) + 1.1 V
VIL Logic low threshold voltage (amplifier enabled) For valid input low, the SHDN pin voltage should be less than the minimum threshold but greater than or equal to V– (V–) + 0.2 (V–) + 0.8 V
tON Amplifier enable time (1) G = +1, VCM = V–, VO = 0.1 × VS / 2 11 µs
tOFF Amplifier disable time (1) VCM = V–, VO = VS / 2  2.5 µs
SHDN pin input bias current (per pin) VS = 2.7 V to 16 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V 500 nA
VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V 150
(1) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.