SLLSF57A August   2022  – April 2024 TMDS1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD and Latch-Up Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1  4-Level Inputs
      2. 7.2.2  I/O Voltage Level Selection
      3. 7.2.3  HPD_OUT
      4. 7.2.4  Lane Control
      5. 7.2.5  Swap
      6. 7.2.6  Linear and Limited Redriver
      7. 7.2.7  Main Link Inputs
      8. 7.2.8  Receiver Equalizer
      9. 7.2.9  CTLE Bypass
      10. 7.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 7.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 7.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 7.2.12 Input Signal Detect
        1. 7.2.12.1 SIGDET_OUT Indicator
      13. 7.2.13 Main Link Outputs
        1. 7.2.13.1 Transmitter Bias
        2. 7.2.13.2 Transmitter Impedance Control
        3. 7.2.13.3 TX Slew Rate Control
        4. 7.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 7.2.13.5 TX Swing Control
        6. 7.2.13.6 Fan-out Buffer
      14. 7.2.14 HDMI DDC Capacitance
      15. 7.2.15 DisplayPort
    3. 7.3 Device Functional Modes
      1. 7.3.1 MODE Control
        1. 7.3.1.1 I2C Mode (MODE = "F")
        2. 7.3.1.2 Pin Strap Modes
          1. 7.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 7.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ)
          3. 7.3.1.2.3 Pin-Strap HDMI 2.1 Function (Mode = "1"): Flexible Rx EQ
          4. 7.3.1.2.4 Pin-Strap HDMI 2.1 Function (Mode = "R"): Flexible Rx EQ and Fan-Out Buffer
      2. 7.3.2 DDC Snoop Feature
        1. 7.3.2.1 HDMI Type
        2. 7.3.2.2 HDMI 2.1 FRL Snoop
      3. 7.3.3 Low Power States
    4. 7.4 Programming
      1. 7.4.1 Pseudocode Examples
        1. 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
        2. 7.4.1.2 Sink Example
      2. 7.4.2 TMDS1204 I2C Address Options
      3. 7.4.3 I2C Target Behavior
    5. 7.5 Register Maps
      1. 7.5.1 TMDS1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Source-Side Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pre-Channel (LAB)
        2. 8.2.2.2 Post-Channel (LCD)
        3. 8.2.2.3 Common Mode Choke
        4. 8.2.2.4 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Typical Sink-Side Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedures
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Supply Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Design Requirements

Table 8-5 Design Parameters
Design ParameterValue
VCC3.3V (±5%)
VIO (1.2V, 1.8V, or 3.3V LVCMOS levels)3.3V
Maximum HDMI 2.1 FRL Datarate (6, 8, 10, or 12Gbps)12Gbps
Pin-strap or I2C mode (if I2C, then MODE = "F"). Pin-strap
Pin Strap Mode.(MODE = "0", "R" or "1").Mode = "1" (Adaptive EQ)
DDC Snoop Feature. (Y/N). Required when in pin strap. Optional in I2C mode.Yes
SWAP function (Y / N). In pin strap mode controlled by SDA/CFG1 pin.No. SDA/CFG1 pin = L.
HPD_IN to HPD_OUT Level Shifter Support (Y / N)No, then HPD_OUT can be left floating.
Pre-Channel Length (Table 8-6 lists the length restrictions)Length = 1 inches; Width = 4 mil. (≅ 1dB at 6GHz insertion loss)
Post-Channel Length (Table 8-6 lists the length restrictions)Length = 6 inches; Width = 4 mil (≅ 6dB at 6GHz insertion loss)
Limited or linear redriver mode?Linear redriver (LINEAR_EN pin = "F") recommended in sink application
TX is DC or AC-coupled to HDMI receptacle? AC-coupled. AC_EN pin = High.
RX EQ (16 possible values. Value chosen based on pre-channel length).EQ1 pin: "0"
ADDR/EQ0 pin: "1"

(2.7dB)

CTLE Map (Map A, Map B or Map C). In pre-strap controlled by CTLEMAP_SEL pin. For Sink application recommend Map B or C.
TX pre-emphasis. In pre-strap mode controlled by TXPRE pin. TX pre-emphasis control not supported in linear redriver mode.Float TXPRE pin.
TX Swing. In pre-strap mode controlled by TXSWG pin.Default TX swing level. Float TXSWG pin.
Fan-out Buffer support (Y / N) Typically only used with a FPGA. If feature needed in pin-strap mode, then MODE must be set to "R".
Table 8-6 Sink Layout and Component Placement Constraints
SymbolParameterConditionMinTypMaxUnits
RESDExternal series resistor between ESD component and TMDS120402.5Ω
LAB(1)(3)PCB trace length from receptacle to TMDS12040.752inches
LINTRA-AB Intra-pair skew from receptacle to TMDS1204 2 mil
LCD(1)PCB trace length from TMDS1204 to sink16inches
LINTRA-CD Intra-pair skew from TMDS1204 to sink 2 mil
LCAP-TXPCB trace length from TMDS1204 to external CAC-TX capacitor0.3inches
LESDPCB trace length from ESD component to receptacle0.5inches
LR_ESDPCB trace length from RESD to ESD component0.25inches
LINTER-PAIR(3) Inter-pair skew between all four channels (D0, D1, D2, and CLK) 0.10 inches
ILPCB PCB trace insertion loss 0.1 0.17 dB / inch /GHz
ZPCB_ABDifferential impedance of LAB90110Ω
ZPCB_CDDifferential impedance of LCD90110Ω
VIAAB Number of vias between receptacle and TMDS1204 1 VIA
VIACD Number of vias between sink and TMDS1204 2 VIA
XTALKDifferential crosstalk between adjacent differential pairs on PCB.≦ 3GHz−24dB
(1) Maximum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss exceeds the maximum limit, then distance needs to be reduced.
(3) Minimum distance assumes PCB trace insertion loss meets ILPCB requirement. If PCB trace insertion loss is less than the minimum limit, then distance needs to be increased.
(3) Calculation of channel length is the sum of LAB and LCD.