SLLSF57A August   2022  – April 2024 TMDS1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD and Latch-Up Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Feature Description
      1. 7.2.1  4-Level Inputs
      2. 7.2.2  I/O Voltage Level Selection
      3. 7.2.3  HPD_OUT
      4. 7.2.4  Lane Control
      5. 7.2.5  Swap
      6. 7.2.6  Linear and Limited Redriver
      7. 7.2.7  Main Link Inputs
      8. 7.2.8  Receiver Equalizer
      9. 7.2.9  CTLE Bypass
      10. 7.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 7.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 7.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 7.2.12 Input Signal Detect
        1. 7.2.12.1 SIGDET_OUT Indicator
      13. 7.2.13 Main Link Outputs
        1. 7.2.13.1 Transmitter Bias
        2. 7.2.13.2 Transmitter Impedance Control
        3. 7.2.13.3 TX Slew Rate Control
        4. 7.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 7.2.13.5 TX Swing Control
        6. 7.2.13.6 Fan-out Buffer
      14. 7.2.14 HDMI DDC Capacitance
      15. 7.2.15 DisplayPort
    3. 7.3 Device Functional Modes
      1. 7.3.1 MODE Control
        1. 7.3.1.1 I2C Mode (MODE = "F")
        2. 7.3.1.2 Pin Strap Modes
          1. 7.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 7.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ)
          3. 7.3.1.2.3 Pin-Strap HDMI 2.1 Function (Mode = "1"): Flexible Rx EQ
          4. 7.3.1.2.4 Pin-Strap HDMI 2.1 Function (Mode = "R"): Flexible Rx EQ and Fan-Out Buffer
      2. 7.3.2 DDC Snoop Feature
        1. 7.3.2.1 HDMI Type
        2. 7.3.2.2 HDMI 2.1 FRL Snoop
      3. 7.3.3 Low Power States
    4. 7.4 Programming
      1. 7.4.1 Pseudocode Examples
        1. 7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
        2. 7.4.1.2 Sink Example
      2. 7.4.2 TMDS1204 I2C Address Options
      3. 7.4.3 I2C Target Behavior
    5. 7.5 Register Maps
      1. 7.5.1 TMDS1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Source-Side Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Pre-Channel (LAB)
        2. 8.2.2.2 Post-Channel (LCD)
        3. 8.2.2.3 Common Mode Choke
        4. 8.2.2.4 ESD Protection
      3. 8.2.3 Application Curves
    3. 8.3 Typical Sink-Side Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedures
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Supply Decoupling
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1.1 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled

When using an external discrete DDC buffer with snooping disabled, this example can be used. In this example, adaptive EQ for HDMI 2.1 is disabled. Also, this example assumes the source only wants to support TXFFE0 level when operating in HDMI 2.1 FRL mode.

This example will initialize the following:

  • Limited redriver mode with DC-coupled output
  • TX slew rate for each data rate
  • CTLE used for each data rate


// (address, data)
// Initial power-on configuration.
(0x0A, 0x05), // Rate snoop disabled and TXFFE controlled by 35h, 41h, and 42h 
(0x0B, 0x23), // 3G and 6G tx slew rate control 
(0x0C, 0x70), // HDMI clock and 8G10G12G TX slew rate control 
(0x0E, 0x97), // HDMI 1.4, 2.0 and 2.1 CTLE selection
(0x11, 0x00), // Disable all four lanes.
(0x09, 0x00), // Take out of PD state. Should be done after initialization is complete.

// Selection between HDMI modes (1.4, 2.0, and 2.1)
switch (HDMI_MODE) {
    case 'HDMI14_165' : // HDMI 1.4 configuration for less than 1.65Gbps
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x20), // Limited mode, DC-coupled TX, 0dB DCG, Term open, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x00), // Clock lane EQ.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x00), // Disable FRL
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI14_340' : // HDMI 1.4 configuration for greater than 1.65Gbps
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x21), // Limited mode, DC-coupled TX, 0dB DCG, Term 300, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x00), // Clock lane EQ.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x00), // Disable FRL
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI20' :  // HDMI 2.0 configuration
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x00), // Clock lane EQ.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x02), // Set TMDS_CLK_RATIO
        (0x31, 0x00), // Disable FRL
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI21_3G' : // HDMI 2.1 3Gbps FRL
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x00), // Clock lane EQ.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x01), // Set to 3G FRL. Only TXFFE0 supported.
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI21_6G_3lane' : // HDMI 2.1 6Gbps FRL 3 lanes
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x00), // Clock lane EQ.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x02), // Set to 6G FRL and 3 lanes. Only TXFFE0 supported.
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI21_6G_4lane' : // HDMI 2.1 6Gbps FRL 4 lanes
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x0Y), // Clock lane EQ. Set to "Y" to desired value.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x03), // Set to 6G FRL and 4 lanes. Only TXFFE0 supported.
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI21_8G' : //HDMI 2.1 8Gbps FRL
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x04), // Set to 8G FRL and 4 lanes. Only TXFFE0 supported.
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI21_10G' : //HDMI 2.1 10Gbps FRL
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x05), // Set to 10G FRL and 4 lanes. Only TXFFE0 supported.
        (0x11, 0x0F), // Enable all four lanes.
        break;
    case 'HDMI21_12G' : //HDMI 2.1 12Gbps FRL
        (0x11, 0x00), // Disable all four lanes.
        (0x0D, 0x23), // Limited mode, DC-coupled TX, 0dB DCG, Term 100, disable CTLE bypass 
        (0x12, 0x03), // Clock lane VOD and TXFFE
        (0x13, 0x0Y), // Clock lane EQ. Set "Y" to desired value.
        (0x14, 0x03), // D0 lane VOD and TXFFE. 
        (0x15, 0x0Y), // D0 lane EQ. Set "Y" to desired value.
        (0x16, 0x03), // D1 lane VOD and TXFFE.
        (0x17, 0x0Y), // D1 lane EQ. Set "Y" to desired value.
        (0x18, 0x03), // D2 lane VOD and TXFFE.
        (0x19, 0x0Y), // D2 lane EQ. Set "Y" to desired value.
        (0x20, 0x00), // Clear TMDS_CLK_RATIO
        (0x31, 0x06), // Set to 12G FRL and 4 lanes. Only TXFFE0 supported.
        (0x11, 0x0F), // Enable all four lanes.
        break;
}