SBOSA50A December   2021  – March 2022 TMP127-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Interface Timing
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Low Power Consumption
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Conversion Mode
      2. 8.4.2 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 Temperature Data Format
      2. 8.5.2 Serial Bus Interface
        1. 8.5.2.1 Communication in Shutdown Mode
        2. 8.5.2.2 Communication in Continuous Conversion Mode
        3. 8.5.2.3 Internal Register Structure
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Read-Only Configuration
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Read/Write Configuration
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 SPI Interface Timing

Over free-air temperature range and VDD = 1.62 V to 5.5 V (unless otherwise noted)
SPI BUS UNIT
MIN MAX
fCLK SCLK frequency 10 MHz
tCLK SCLK Period 100 ns
tLEAD Falling edge of CS to rising edge of SCLK setup time 100 ns
tLAG Rising edge of SCLK to rising edge of CS setup time 20 ns
tSU SIO to SCLK rising edge setup time 10 ns
tHOLD SIO hold time after rising edge of SCLK 20 ns
tVALID Time from falling edge of SLCK to valid SIO data 35 ns
tSIO(DIS) Time from rising edge of CS to SIO high-impedance 200 ns
tSIO(EN) Time from falling edge of CS to SIO low impedance 70 ns
tRISE SIO, SCLK, CS rise time 100 ns
tFALL SIO, SCLK, CS fall time 100 ns
tINTERFRAME Delay between two SPI communication sequences (CS high) 100 ns
tINITIATION Delay between valid VDD volage and initial SPI communication 0.5 ms