SBOSA15B September   2022  – January 2025 TMP1827

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Description (cont.)
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  1-Wire® Interface Timing
    7. 7.7  Security Engine Characteristics
    8. 7.8  EEPROM Characteristics
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Up
      2. 8.3.2  Power Mode Switch
      3. 8.3.3  Bus Pullup Resistor
      4. 8.3.4  Temperature Results
      5. 8.3.5  Temperature Offset
      6. 8.3.6  Temperature Alert
      7. 8.3.7  Standard Device Address
        1. 8.3.7.1 Unique 64-Bit Device Address and ID
      8. 8.3.8  Flexible Device Address
        1. 8.3.8.1 Non-Volatile Short Address
        2. 8.3.8.2 IO Hardware Address
        3. 8.3.8.3 Resistor Address
        4. 8.3.8.4 Combined IO and Resistor Address
      9. 8.3.9  CRC Generation
      10. 8.3.10 Functional Register Map
      11. 8.3.11 User Memory Map
      12. 8.3.12 SHA-256-HMAC Authentication Block
      13. 8.3.13 Bit Communication
        1. 8.3.13.1 Host Write, Device Read
        2. 8.3.13.2 Host Read, Device Write
      14. 8.3.14 Bus Speed
      15. 8.3.15 NIST Traceability
    4. 8.4 Device Functional Modes
      1. 8.4.1 Conversion Modes
        1. 8.4.1.1 Basic One-Shot Conversion Mode
        2. 8.4.1.2 Auto Conversion Mode
        3. 8.4.1.3 Stacked Conversion Mode
        4. 8.4.1.4 Continuous Conversion Mode
      2. 8.4.2 Alert Function
        1. 8.4.2.1 Alert Mode
        2. 8.4.2.2 Comparator Mode
      3. 8.4.3 1-Wire® Interface Communication
        1. 8.4.3.1 Bus Reset Phase
        2. 8.4.3.2 Address Phase
          1. 8.4.3.2.1 READADDR (33h)
          2. 8.4.3.2.2 MATCHADDR (55h)
          3. 8.4.3.2.3 SEARCHADDR (F0h)
          4. 8.4.3.2.4 ALERTSEARCH (ECh)
          5. 8.4.3.2.5 SKIPADDR (CCh)
          6. 8.4.3.2.6 OVD SKIPADDR (3Ch)
          7. 8.4.3.2.7 OVD MATCHADDR (69h)
          8. 8.4.3.2.8 FLEXADDR (0Fh)
        3. 8.4.3.3 Function Phase
          1. 8.4.3.3.1  CONVERTTEMP (44h)
          2. 8.4.3.3.2  WRITE SCRATCHPAD-1 (4Eh)
          3. 8.4.3.3.3  READ SCRATCHPAD-1 (BEh)
          4. 8.4.3.3.4  COPY SCRATCHPAD-1 (48h)
          5. 8.4.3.3.5  WRITE SCRATCHPAD-2 (0Fh)
          6. 8.4.3.3.6  READ SCRATCHPAD-2 (AAh)
          7. 8.4.3.3.7  COPY SCRATCHPAD-2 (55h)
          8. 8.4.3.3.8  READ EEPROM (F0h)
          9. 8.4.3.3.9  GPIO WRITE (A5h)
          10. 8.4.3.3.10 GPIO READ (F5h)
      4. 8.4.4 NVM Operations
        1. 8.4.4.1 Programming User Data
        2. 8.4.4.2 Register and Memory Protection
          1. 8.4.4.2.1 Scratchpad-1 Register Protection
          2. 8.4.4.2.2 User Memory Protection
    5. 8.5 Programming
      1. 8.5.1 Single Device Temperature Conversion and Read
      2. 8.5.2 Multiple Device Temperature Conversion and Read
      3. 8.5.3 Register Scratchpad-1 Update and Commit
      4. 8.5.4 Single Device EEPROM Programming and Verify
      5. 8.5.5 Single Device EEPROM Page Lock Operation
      6. 8.5.6 Multiple Device IO Read
      7. 8.5.7 Multiple Device IO Write
    6. 8.6 Register Map
      1. 8.6.1  Temperature Result LSB Register (Scratchpad-1 offset = 00h) [reset = 00h]
      2. 8.6.2  Temperature Result MSB Register (Scratchpad-1 offset = 01h) [reset = 00h]
      3. 8.6.3  Status Register (Scratchpad-1 offset = 02h) [reset = 3Ch]
      4. 8.6.4  Device Configuration-1 Register (Scratchpad-1 offset = 04h) [reset = 70h]
      5. 8.6.5  Device Configuration-2 Register (Scratchpad-1 offset = 05h) [reset = 80h]
      6. 8.6.6  Short Address Register (Scratchpad-1 offset = 06h) [reset = 00h]
      7. 8.6.7  Temperature Alert Low LSB Register (Scratchpad-1 offset = 08h) [reset = 00h]
      8. 8.6.8  Temperature Alert Low MSB Register (Scratchpad-1 offset = 09h) [reset = 00h]
      9. 8.6.9  Temperature Alert High LSB Register (Scratchpad-1 offset = 0Ah) [reset = F0h]
      10. 8.6.10 Temperature Alert High MSB Register (Scratchpad-1 offset = 0Bh) [reset = 07h]
      11. 8.6.11 Temperature Offset LSB Register (Scratchpad-1 offset = 0Ch) [reset = 00h]
      12. 8.6.12 Temperature Offset MSB Register (Scratchpad-1 offset = 0Dh) [reset = 00h]
      13. 8.6.13 IO Read Register [reset = F0h]
      14. 8.6.14 IO Configuration Register [reset = 00h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Bus Powered Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Supply Powered Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 UART Interface for Communication
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1 Layout Guidelines

Place the power-supply bypass capacitor as close as possible to the supply and ground pins when in supply powered mode (see Figure 9-4). The recommended value of the capacitor is 0.1 µF. The open-drain SDQ pin requires an external pullup resistor which must not be higher than RPUR.

When in bus powered mode, only the external pullup resistor is required for the open-drain SDQ pin. As shown in Figure 9-5, TI recommends to place a 20-KΩ pullup resistor when connecting IO to SDQ pin to avoid shorting the SDQ to GND in case the IO is configured as an output and driven low (see Figure 9-6). The ADDR pin resistor uses very low current to decode the short address and must be placed close to the device, if possible. Take care to avoid leakage currents to prevent incorrect decoding.