SPRS377F September   2008  – June 2014 TMS320C6745 , TMS320C6747

PRODUCTION DATA.  

  1. 1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6747 Top Level Memory Map
      2. Table 3-5 C6745 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 General Purpose Input Output (GPIO)
      21. 3.6.21 Reserved and No Connect
      22. 3.6.22 Supply and Ground
      23. 3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-9  Timing Requirements for GPIO Inputs (see )
        2. Table 6-10 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-11 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface A (EMIFA) Registers
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA SDRAM Interface Timing Requirements
        2. Table 6-20 EMIFA SDRAM Interface Switching Characteristics
        3. Table 6-21 EMIFA Asynchronous Memory Timing Requirements
        4. Table 6-22 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-26 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-27 EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range
        3. Table 6-28 EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-32 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-33 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-41 Timing Requirements for MDIO Input (see and )
        2. Table 6-42 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 McASP0 Timing Requirements
          2. Table 6-48 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-49 McASP1 Timing Requirements
          2. Table 6-50 McASP1 Switching Characteristics
        3. 6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
          1. Table 6-51 McASP2 Timing Requirements
          2. Table 6-52 McASP2 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-54 General Timing Requirements for SPI0 Master Modes
          2. Table 6-55 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-56 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-57 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-58 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-59 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-60 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-61 Additional SPI0 Slave Timings, 5-Pin Option
          9. Table 6-62 General Timing Requirements for SPI1 Master Modes
          10. Table 6-63 General Timing Requirements for SPI1 Slave Modes
          11. Table 6-64 Additional SPI1 Master Timings, 4-Pin Enable Option
          12. Table 6-65 Additional SPI1 Master Timings, 4-Pin Chip Select Option
          13. Table 6-66 Additional SPI1 Master Timings, 5-Pin Option
          14. Table 6-67 Additional SPI1 Slave Timings, 4-Pin Enable Option
          15. Table 6-68 Additional SPI1 Slave Timings, 4-Pin Chip Select Option
          16. Table 6-69 Additional SPI1 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-71 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-72 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-74 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-75 eQEP Switching Characteristics
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-77 eHRPWM Timing Requirements
        2. Table 6-78 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 LCD Controller
      1. 6.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.21.2 LCD Raster Mode
        1. Table 6-84 LCD Raster Mode Timing
    22. 6.22 Timers
      1. 6.22.1 Timer Electrical Data/Timing
        1. Table 6-86 Timing Requirements for Timer Input (see )
        2. Table 6-87 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    23. 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.23.1 I2C Device-Specific Information
      2. 6.23.2 I2C Peripheral Registers Description(s)
      3. 6.23.3 I2C Electrical Data/Timing
        1. 6.23.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-89 I2C Input Timing Requirements
          2. Table 6-90 I2C Switching Characteristics
    24. 6.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.24.1 UART Peripheral Registers Description(s)
      2. 6.24.2 UART Electrical Data/Timing
        1. Table 6-92 Timing Requirements for UARTx Receive (see )
        2. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    25. 6.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1
      2. 6.25.1     USB1 Unused Signal Configuration
    26. 6.26 USB0 OTG (USB2.0 OTG)
      1. 6.26.1 USB2.0 Electrical Data/Timing
        1. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see )
      2. 6.26.2 USB0 Unused Signal Configuration
    27. 6.27 Host-Port Interface (UHPI)
      1. 6.27.1 HPI Device-Specific Information
      2. 6.27.2 HPI Peripheral Register Description(s)
      3. 6.27.3 HPI Electrical Data/Timing
        1. Table 6-99  Timing Requirements for Host-Port Interface Cycles
        2. Table 6-100 Switching Characteristics for Host-Port Interface Cycles
    28. 6.28 Power and Sleep Controller (PSC)
      1. 6.28.1 Power Domain and Module Topology
        1. 6.28.1.1 Power Domain States
        2. 6.28.1.2 Module States
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 JTAG 1149.1 Boundary Scan Considerations
    31. 6.31 IEEE 1149.1 JTAG
      1. 6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
      2. 6.31.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-115 Timing Requirements for JTAG Test Port (see )
        2. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
    32. 6.32 Real Time Clock (RTC)
      1. 6.32.1 Clock Source
      2. 6.32.2 Real-Time Clock Registers
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Related Links
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZKB|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

C674x DSP CPU Description

The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core.

Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L Unit (or Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

  • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
  • Compact Instructions - The native instruction size for the C6000™ devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.
  • Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.
  • Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).
  • Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.
  • Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents:

  • TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
  • TMS320C64x Technical Overview (SPRU395)

TMS320C6745 TMS320C6747 dg_cpu_prs271.gifFigure 3-2 TMS320C674x CPU (DSP Core) Data Paths