SPRS377F September   2008  – June 2014 TMS320C6745 , TMS320C6747

PRODUCTION DATA.  

  1. 1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6747 Top Level Memory Map
      2. Table 3-5 C6745 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 General Purpose Input Output (GPIO)
      21. 3.6.21 Reserved and No Connect
      22. 3.6.22 Supply and Ground
      23. 3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-9  Timing Requirements for GPIO Inputs (see )
        2. Table 6-10 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-11 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface A (EMIFA) Registers
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA SDRAM Interface Timing Requirements
        2. Table 6-20 EMIFA SDRAM Interface Switching Characteristics
        3. Table 6-21 EMIFA Asynchronous Memory Timing Requirements
        4. Table 6-22 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-26 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-27 EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range
        3. Table 6-28 EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-32 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-33 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-41 Timing Requirements for MDIO Input (see and )
        2. Table 6-42 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 McASP0 Timing Requirements
          2. Table 6-48 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-49 McASP1 Timing Requirements
          2. Table 6-50 McASP1 Switching Characteristics
        3. 6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
          1. Table 6-51 McASP2 Timing Requirements
          2. Table 6-52 McASP2 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-54 General Timing Requirements for SPI0 Master Modes
          2. Table 6-55 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-56 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-57 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-58 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-59 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-60 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-61 Additional SPI0 Slave Timings, 5-Pin Option
          9. Table 6-62 General Timing Requirements for SPI1 Master Modes
          10. Table 6-63 General Timing Requirements for SPI1 Slave Modes
          11. Table 6-64 Additional SPI1 Master Timings, 4-Pin Enable Option
          12. Table 6-65 Additional SPI1 Master Timings, 4-Pin Chip Select Option
          13. Table 6-66 Additional SPI1 Master Timings, 5-Pin Option
          14. Table 6-67 Additional SPI1 Slave Timings, 4-Pin Enable Option
          15. Table 6-68 Additional SPI1 Slave Timings, 4-Pin Chip Select Option
          16. Table 6-69 Additional SPI1 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-71 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-72 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-74 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-75 eQEP Switching Characteristics
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-77 eHRPWM Timing Requirements
        2. Table 6-78 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 LCD Controller
      1. 6.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.21.2 LCD Raster Mode
        1. Table 6-84 LCD Raster Mode Timing
    22. 6.22 Timers
      1. 6.22.1 Timer Electrical Data/Timing
        1. Table 6-86 Timing Requirements for Timer Input (see )
        2. Table 6-87 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    23. 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.23.1 I2C Device-Specific Information
      2. 6.23.2 I2C Peripheral Registers Description(s)
      3. 6.23.3 I2C Electrical Data/Timing
        1. 6.23.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-89 I2C Input Timing Requirements
          2. Table 6-90 I2C Switching Characteristics
    24. 6.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.24.1 UART Peripheral Registers Description(s)
      2. 6.24.2 UART Electrical Data/Timing
        1. Table 6-92 Timing Requirements for UARTx Receive (see )
        2. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    25. 6.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1
      2. 6.25.1     USB1 Unused Signal Configuration
    26. 6.26 USB0 OTG (USB2.0 OTG)
      1. 6.26.1 USB2.0 Electrical Data/Timing
        1. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see )
      2. 6.26.2 USB0 Unused Signal Configuration
    27. 6.27 Host-Port Interface (UHPI)
      1. 6.27.1 HPI Device-Specific Information
      2. 6.27.2 HPI Peripheral Register Description(s)
      3. 6.27.3 HPI Electrical Data/Timing
        1. Table 6-99  Timing Requirements for Host-Port Interface Cycles
        2. Table 6-100 Switching Characteristics for Host-Port Interface Cycles
    28. 6.28 Power and Sleep Controller (PSC)
      1. 6.28.1 Power Domain and Module Topology
        1. 6.28.1.1 Power Domain States
        2. 6.28.1.2 Module States
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 JTAG 1149.1 Boundary Scan Considerations
    31. 6.31 IEEE 1149.1 JTAG
      1. 6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
      2. 6.31.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-115 Timing Requirements for JTAG Test Port (see )
        2. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
    32. 6.32 Real Time Clock (RTC)
      1. 6.32.1 Clock Source
      2. 6.32.2 Real-Time Clock Registers
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Related Links
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZKB|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.14.1 EMAC Peripheral Register Description(s)

Table 6-34 Ethernet Media Access Controller (EMAC) Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3000 TXREV Transmit Revision Register
0x01E2 3004 TXCONTROL Transmit Control Register
0x01E2 3008 TXTEARDOWN Transmit Teardown Register
0x01E2 3010 RXREV Receive Revision Register
0x01E2 3014 RXCONTROL Receive Control Register
0x01E2 3018 RXTEARDOWN Receive Teardown Register
0x01E2 3080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register
0x01E2 3084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register
0x01E2 3088 TXINTMASKSET Transmit Interrupt Mask Set Register
0x01E2 308C TXINTMASKCLEAR Transmit Interrupt Clear Register
0x01E2 3090 MACINVECTOR MAC Input Vector Register
0x01E2 3094 MACEOIVECTOR MAC End Of Interrupt Vector Register
0x01E2 30A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register
0x01E2 30A4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register
0x01E2 30A8 RXINTMASKSET Receive Interrupt Mask Set Register
0x01E2 30AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register
0x01E2 30B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register
0x01E2 30B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register
0x01E2 30B8 MACINTMASKSET MAC Interrupt Mask Set Register
0x01E2 30BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register
0x01E2 3100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register
0x01E2 3104 RXUNICASTSET Receive Unicast Enable Set Register
0x01E2 3108 RXUNICASTCLEAR Receive Unicast Clear Register
0x01E2 310C RXMAXLEN Receive Maximum Length Register
0x01E2 3110 RXBUFFEROFFSET Receive Buffer Offset Register
0x01E2 3114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
0x01E2 3120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
0x01E2 3124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register
0x01E2 3128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register
0x01E2 312C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register
0x01E2 3130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register
0x01E2 3134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register
0x01E2 3138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register
0x01E2 313C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register
0x01E2 3140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register
0x01E2 3144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register
0x01E2 3148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register
0x01E2 314C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register
0x01E2 3150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register
0x01E2 3154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register
0x01E2 3158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register
0x01E2 315C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register
0x01E2 3160 MACCONTROL MAC Control Register
0x01E2 3164 MACSTATUS MAC Status Register
0x01E2 3168 EMCONTROL Emulation Control Register
0x01E2 316C FIFOCONTROL FIFO Control Register
0x01E2 3170 MACCONFIG MAC Configuration Register
0x01E2 3174 SOFTRESET Soft Reset Register
0x01E2 31D0 MACSRCADDRLO MAC Source Address Low Bytes Register
0x01E2 31D4 MACSRCADDRHI MAC Source Address High Bytes Register
0x01E2 31D8 MACHASH1 MAC Hash Address Register 1
0x01E2 31DC MACHASH2 MAC Hash Address Register 2
0x01E2 31E0 BOFFTEST Back Off Test Register
0x01E2 31E4 TPACETEST Transmit Pacing Algorithm Test Register
0x01E2 31E8 RXPAUSE Receive Pause Timer Register
0x01E2 31EC TXPAUSE Transmit Pause Timer Register
0x01E2 3200 - 0x01E2 32FC (see Table 6-35) EMAC Statistics Registers
0x01E2 3500 MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Matching
0x01E2 3504 MACADDRHI MAC Address High Bytes Register, Used in Receive Address Matching
0x01E2 3508 MACINDEX MAC Index Register
0x01E2 3600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register
0x01E2 360C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register
0x01E2 361C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register
0x01E2 362C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register
0x01E2 363C RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3640 TX0CP Transmit Channel 0 Completion Pointer Register
0x01E2 3644 TX1CP Transmit Channel 1 Completion Pointer Register
0x01E2 3648 TX2CP Transmit Channel 2 Completion Pointer Register
0x01E2 364C TX3CP Transmit Channel 3 Completion Pointer Register
0x01E2 3650 TX4CP Transmit Channel 4 Completion Pointer Register
0x01E2 3654 TX5CP Transmit Channel 5 Completion Pointer Register
0x01E2 3658 TX6CP Transmit Channel 6 Completion Pointer Register
0x01E2 365C TX7CP Transmit Channel 7 Completion Pointer Register
0x01E2 3660 RX0CP Receive Channel 0 Completion Pointer Register
0x01E2 3664 RX1CP Receive Channel 1 Completion Pointer Register
0x01E2 3668 RX2CP Receive Channel 2 Completion Pointer Register
0x01E2 366C RX3CP Receive Channel 3 Completion Pointer Register
0x01E2 3670 RX4CP Receive Channel 4 Completion Pointer Register
0x01E2 3674 RX5CP Receive Channel 5 Completion Pointer Register
0x01E2 3678 RX6CP Receive Channel 6 Completion Pointer Register
0x01E2 367C RX7CP Receive Channel 7 Completion Pointer Register

Table 6-35 EMAC Statistics Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3200 RXGOODFRAMES Good Receive Frames Register
0x01E2 3204 RXBCASTFRAMES Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3208 RXMCASTFRAMES Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 320C RXPAUSEFRAMES Pause Receive Frames Register
0x01E2 3210 RXCRCERRORS Receive CRC Errors Register
(Total number of frames received with CRC errors)
0x01E2 3214 RXALIGNCODEERRORS Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
0x01E2 3218 RXOVERSIZED Receive Oversized Frames Register
(Total number of oversized frames received)
0x01E2 321C RXJABBER Receive Jabber Frames Register
(Total number of jabber frames received)
0x01E2 3220 RXUNDERSIZED Receive Undersized Frames Register
(Total number of undersized frames received)
0x01E2 3224 RXFRAGMENTS Receive Frame Fragments Register
0x01E2 3228 RXFILTERED Filtered Receive Frames Register
0x01E2 322C RXQOSFILTERED Received QOS Filtered Frames Register
0x01E2 3230 RXOCTETS Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3234 TXGOODFRAMES Good Transmit Frames Register
(Total number of good frames transmitted)
0x01E2 3238 TXBCASTFRAMES Broadcast Transmit Frames Register
0x01E2 323C TXMCASTFRAMES Multicast Transmit Frames Register
0x01E2 3240 TXPAUSEFRAMES Pause Transmit Frames Register
0x01E2 3244 TXDEFERRED Deferred Transmit Frames Register
0x01E2 3248 TXCOLLISION Transmit Collision Frames Register
0x01E2 324C TXSINGLECOLL Transmit Single Collision Frames Register
0x01E2 3250 TXMULTICOLL Transmit Multiple Collision Frames Register
0x01E2 3254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register
0x01E2 3258 TXLATECOLL Transmit Late Collision Frames Register
0x01E2 325C TXUNDERRUN Transmit Underrun Error Register
0x01E2 3260 TXCARRIERSENSE Transmit Carrier Sense Errors Register
0x01E2 3264 TXOCTETS Transmit Octet Frames Register
0x01E2 3268 FRAME64 Transmit and Receive 64 Octet Frames Register
0x01E2 326C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register
0x01E2 3270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register
0x01E2 3274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register
0x01E2 3278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register
0x01E2 327C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register
0x01E2 3280 NETOCTETS Network Octet Frames Register
0x01E2 3284 RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register
0x01E2 3288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register
0x01E2 328C RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Register

Table 6-36 EMAC Control Module Registers

BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 2000 REV EMAC Control Module Revision Register
0x01E2 2004 SOFTRESET EMAC Control Module Software Reset Register
0x01E2 200C INTCONTROL EMAC Control Module Interrupt Control Register
0x01E2 2010 C0RXTHRESHEN EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
0x01E2 2014 C0RXEN EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
0x01E2 2018 C0TXEN EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
0x01E2 201C C0MISCEN EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
0x01E2 2020 C1RXTHRESHEN EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
0x01E2 2024 C1RXEN EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
0x01E2 2028 C1TXEN EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
0x01E2 202C C1MISCEN EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
0x01E2 2030 C2RXTHRESHEN EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
0x01E2 2034 C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
0x01E2 2038 C2TXEN EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
0x01E2 203C C2MISCEN EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
0x01E2 2040 C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
0x01E2 2044 C0RXSTAT EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
0x01E2 2048 C0TXSTAT EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
0x01E2 204C C0MISCSTAT EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
0x01E2 2050 C1RXTHRESHSTAT EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
0x01E2 2054 C1RXSTAT EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
0x01E2 2058 C1TXSTAT EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
0x01E2 205C C1MISCSTAT EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
0x01E2 2060 C2RXTHRESHSTAT EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
0x01E2 2064 C2RXSTAT EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
0x01E2 2068 C2TXSTAT EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
0x01E2 206C C2MISCSTAT EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
0x01E2 2070 C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
0x01E2 2074 C0TXIMAX EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
0x01E2 2078 C1RXIMAX EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
0x01E2 207C C1TXIMAX EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
0x01E2 2080 C2RXIMAX EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
0x01E2 2084 C2TXIMAX EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register

Table 6-37 EMAC Control Module RAM

BYTE ADRESS REGISTER DESCRIPTION
0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory

Table 6-38 RMII Timing Requirements

No. PARAMETER MIN TYP MAX UNIT
1 tc(REFCLK) Cycle Time, RMII_MHZ_50_CLK 20 ns
2 tw(REFCLKH) Pulse Width, RMII_MHZ_50_CLK High 7 13 ns
3 tw(REFCLKL) Pulse Width, RMII_MHZ_50_CLK Low 7 13 ns
6 tsu(RXD-REFCLK) Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High 4 ns
7 th(REFCLK-RXD) Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High 2 ns
8 tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High 4 ns
9 th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High 2 ns
10 tsu(RXER-REFCLK) Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High 4 ns
11 th(REFCLKR-RXER) Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High 2 ns

Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.

Table 6-39 RMII Switching Characteristics

No. PARAMETER MIN TYP MAX UNIT
4 td(REFCLK-TXD) Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid 2.5 13 ns
5 td(REFCLK-TXEN) Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid 2.5 13 ns
TMS320C6745 TMS320C6747 rmii_tmng1_prs483.gifFigure 6-30 RMII Timing Diagram