SPRSP25A June 2018 – July 2018 TMS320F28035-EP
To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. Driving an external load with the internal VREG is not supported.