SPRSP85C April   2024  – June 2025 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pin Multiplexing
      1. 5.4.1 GPIO Muxed Pins
      2. 5.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
      4. 5.4.4 GPIO Input X-BAR
      5. 5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 5.5 Pins With Internal Pullup and Pulldown
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption - VREG Enable - Internal Supply
      2. 6.5.2 System Current Consumption - VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Reducing Current Consumption
        1. 6.5.4.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Special Considerations for 5V Fail-Safe Pins
    8. 6.8  Thermal Resistance Characteristics for PDT Package
    9. 6.9  Thermal Resistance Characteristics for PZ Package
    10. 6.10 Thermal Resistance Characteristics for PNA Package
    11. 6.11 Thermal Resistance Characteristics for PM Package
    12. 6.12 Thermal Resistance Characteristics for RSH Package
    13. 6.13 Thermal Design Considerations
    14. 6.14 System
      1. 6.14.1  Power Management Module (PMM)
        1. 6.14.1.1 Introduction
        2. 6.14.1.2 Overview
          1. 6.14.1.2.1 Power Rail Monitors
            1. 6.14.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.14.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.14.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.14.1.2.2 External Supervisor Usage
          3. 6.14.1.2.3 Delay Blocks
          4. 6.14.1.2.4 Internal VDD LDO Voltage Regulator (VREG)
          5. 6.14.1.2.5 VREGENZ
        3. 6.14.1.3 External Components
          1. 6.14.1.3.1 Decoupling Capacitors
            1. 6.14.1.3.1.1 VDDIO Decoupling
            2. 6.14.1.3.1.2 VDD Decoupling
        4. 6.14.1.4 Power Sequencing
          1. 6.14.1.4.1 Supply Pins Ganging
          2. 6.14.1.4.2 Signal Pins Power Sequence
          3. 6.14.1.4.3 Supply Pins Power Sequence
            1. 6.14.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.14.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.14.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.14.1.4.3.4 Supply Slew Rate
        5. 6.14.1.5 Power Management Module Electrical Data and Timing
          1. 6.14.1.5.1 Power Management Module Operating Conditions
          2. 6.14.1.5.2 Power Management Module Characteristics
      2. 6.14.2  Reset Timing
        1. 6.14.2.1 Reset Sources
        2. 6.14.2.2 Reset Electrical Data and Timing
          1. 6.14.2.2.1 Reset - XRSn - Timing Requirements
          2. 6.14.2.2.2 Reset - XRSn - Switching Characteristics
          3. 6.14.2.2.3 Reset Timing Diagrams
      3. 6.14.3  Clock Specifications
        1. 6.14.3.1 Clock Sources
        2. 6.14.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.14.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.14.3.2.1.1 Input Clock Frequency
            2. 6.14.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.14.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source - Not a Crystal
            4. 6.14.3.2.1.4 X1 Timing Requirements
            5. 6.14.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.14.3.2.1.6 APLL Characteristics
            7. 6.14.3.2.1.7 XCLKOUT Switching Characteristics - PLL Bypassed or Enabled
            8. 6.14.3.2.1.8 Internal Clock Frequencies
        3. 6.14.3.3 Input Clocks and PLLs
        4. 6.14.3.4 XTAL Oscillator
          1. 6.14.3.4.1 Introduction
          2. 6.14.3.4.2 Overview
            1. 6.14.3.4.2.1 Electrical Oscillator
              1. 6.14.3.4.2.1.1 Modes of Operation
                1. 6.14.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.14.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.14.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.14.3.4.2.2 Quartz Crystal
            3. 6.14.3.4.2.3 GPIO Modes of Operation
          3. 6.14.3.4.3 Functional Operation
            1. 6.14.3.4.3.1 ESR – Effective Series Resistance
            2. 6.14.3.4.3.2 Rneg – Negative Resistance
            3. 6.14.3.4.3.3 Start-up Time
              1. 6.14.3.4.3.3.1 X1/X2 Precondition
            4. 6.14.3.4.3.4 DL – Drive Level
          4. 6.14.3.4.4 How to Choose a Crystal
          5. 6.14.3.4.5 Testing
          6. 6.14.3.4.6 Common Problems and Debug Tips
          7. 6.14.3.4.7 Crystal Oscillator Specifications
            1. 6.14.3.4.7.1 Crystal Equivalent Series Resistance (ESR) Requirements
            2. 6.14.3.4.7.2 Crystal Oscillator Parameters
            3. 6.14.3.4.7.3 Crystal Oscillator Electrical Characteristics
        5. 6.14.3.5 Internal Oscillators
          1. 6.14.3.5.1 INTOSC Characteristics
      4. 6.14.4  Flash Parameters
        1. 6.14.4.1 Flash Parameters 
      5. 6.14.5  RAM Specifications
      6. 6.14.6  ROM Specifications
      7. 6.14.7  Emulation/JTAG
        1. 6.14.7.1 JTAG Electrical Data and Timing
          1. 6.14.7.1.1 JTAG Timing Requirements
          2. 6.14.7.1.2 JTAG Switching Characteristics
          3. 6.14.7.1.3 JTAG Timing Diagram
        2. 6.14.7.2 cJTAG Electrical Data and Timing
          1. 6.14.7.2.1 cJTAG Timing Requirements
          2. 6.14.7.2.2 cJTAG Switching Characteristics
          3. 6.14.7.2.3 cJTAG Timing Diagram
      8. 6.14.8  GPIO Electrical Data and Timing
        1. 6.14.8.1 GPIO – Output Timing
          1. 6.14.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.14.8.1.2 General-Purpose Output Timing Diagram
        2. 6.14.8.2 GPIO – Input Timing
          1. 6.14.8.2.1 General-Purpose Input Timing Requirements
          2. 6.14.8.2.2 Sampling Mode
        3. 6.14.8.3 Sampling Window Width for Input Signals
      9. 6.14.9  Interrupts
        1. 6.14.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.14.9.1.1 External Interrupt Timing Requirements
          2. 6.14.9.1.2 External Interrupt Switching Characteristics
          3. 6.14.9.1.3 External Interrupt Timing
      10. 6.14.10 Low-Power Modes
        1. 6.14.10.1 Clock-Gating Low-Power Modes
        2. 6.14.10.2 Low-Power Mode Wake-up Timing
          1. 6.14.10.2.1 IDLE Mode Timing Requirements
          2. 6.14.10.2.2 IDLE Mode Switching Characteristics
          3. 6.14.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.14.10.2.4 STANDBY Mode Timing Requirements
          5. 6.14.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.14.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.14.10.2.7 HALT Mode Timing Requirements
          8. 6.14.10.2.8 HALT Mode Switching Characteristics
          9. 6.14.10.2.9 HALT Entry and Exit Timing Diagram
    15. 6.15 Analog Peripherals
      1. 6.15.1 Block Diagram
      2. 6.15.2 Analog Pins and Internal Connections
      3. 6.15.3 Analog Signal Descriptions
      4. 6.15.4 Analog-to-Digital Converter (ADC)
        1. 6.15.4.1 ADC Configurability
          1. 6.15.4.1.1 Signal Mode
        2. 6.15.4.2 ADC Electrical Data and Timing
          1. 6.15.4.2.1 ADC Operating Conditions
          2. 6.15.4.2.2 ADC Characteristics
          3. 6.15.4.2.3 ADC INL and DNL
          4. 6.15.4.2.4 ADC Performance Per Pin
          5. 6.15.4.2.5 ADC Input Model
          6. 6.15.4.2.6 ADC Timing Diagrams
      5. 6.15.5 Temperature Sensor
        1. 6.15.5.1 Temperature Sensor Electrical Data and Timing
          1. 6.15.5.1.1 Temperature Sensor Characteristics
      6. 6.15.6 Comparator Subsystem (CMPSS)
        1. 6.15.6.1 CMPx_DACL
        2. 6.15.6.2 CMPSS Connectivity Diagram
        3. 6.15.6.3 Block Diagram
        4. 6.15.6.4 CMPSS Electrical Data and Timing
          1. 6.15.6.4.1 CMPSS Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.15.6.4.2 CMPSS DAC Static Electrical Characteristics
          4. 6.15.6.4.3 CMPSS Illustrative Graphs
          5. 6.15.6.4.4 Buffered Output from CMPx_DACL Operating Conditions
          6. 6.15.6.4.5 Buffered Output from CMPx_DACL Electrical Characteristics
      7. 6.15.7 Buffered Digital-to-Analog Converter (DAC)
        1. 6.15.7.1 Buffered DAC Electrical Data and Timing
          1. 6.15.7.1.1 Buffered DAC Operating Conditions
          2. 6.15.7.1.2 Buffered DAC Electrical Characteristics
      8. 6.15.8 Programmable Gain Amplifier (PGA)
        1. 6.15.8.1 PGA Electrical Data and Timing
          1. 6.15.8.1.1 PGA Operating Conditions
          2. 6.15.8.1.2 PGA Characteristics
    16. 6.16 Control Peripherals
      1. 6.16.1 Enhanced Pulse Width Modulator (ePWM)
        1. 6.16.1.1 Control Peripherals Synchronization
        2. 6.16.1.2 ePWM Electrical Data and Timing
          1. 6.16.1.2.1 ePWM Timing Requirements
          2. 6.16.1.2.2 ePWM Switching Characteristics
          3. 6.16.1.2.3 Trip-Zone Input Timing
            1. 6.16.1.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.16.1.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      2. 6.16.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.16.2.1 HRPWM Electrical Data and Timing
          1. 6.16.2.1.1 High-Resolution PWM Characteristics
      3. 6.16.3 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.16.3.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.16.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
      4. 6.16.4 Enhanced Capture (eCAP)
        1. 6.16.4.1 eCAP Block Diagram
        2. 6.16.4.2 eCAP Synchronization
        3. 6.16.4.3 eCAP Electrical Data and Timing
          1. 6.16.4.3.1 eCAP Timing Requirements
          2. 6.16.4.3.2 eCAP Switching Characteristics
      5. 6.16.5 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.16.5.1 eQEP Electrical Data and Timing
          1. 6.16.5.1.1 eQEP Timing Requirements
          2. 6.16.5.1.2 eQEP Switching Characteristics
    17. 6.17 Communications Peripherals
      1. 6.17.1 Modular Controller Area Network (MCAN)
      2. 6.17.2 Inter-Integrated Circuit (I2C)
        1. 6.17.2.1 I2C Electrical Data and Timing
          1. 6.17.2.1.1 I2C Timing Requirements
          2. 6.17.2.1.2 I2C Switching Characteristics
          3. 6.17.2.1.3 I2C Timing Diagram
      3. 6.17.3 Power Management Bus (PMBus) Interface
        1. 6.17.3.1 PMBus Electrical Data and Timing
          1. 6.17.3.1.1 PMBus Electrical Characteristics
          2. 6.17.3.1.2 PMBus Fast Plus Mode Switching Characteristics
          3. 6.17.3.1.3 PMBus Fast Mode Switching Characteristics
          4. 6.17.3.1.4 PMBus Standard Mode Switching Characteristics
      4. 6.17.4 Serial Communications Interface (SCI)
      5. 6.17.5 Serial Peripheral Interface (SPI)
        1. 6.17.5.1 SPI Controller Mode Timings
          1. 6.17.5.1.1 SPI Controller Mode Timing Requirements
          2. 6.17.5.1.2 SPI Controller Mode Switching Characteristics - Clock Phase 0
          3. 6.17.5.1.3 SPI Controller Mode Switching Characteristics - Clock Phase 1
          4. 6.17.5.1.4 SPI Controller Mode Timing Diagrams
        2. 6.17.5.2 SPI Peripheral Mode Timings
          1. 6.17.5.2.1 SPI Peripheral Mode Timing Requirements
          2. 6.17.5.2.2 SPI Peripheral Mode Switching Characteristics
          3. 6.17.5.2.3 SPI Peripheral Mode Timing Diagrams
      6. 6.17.6 Local Interconnect Network (LIN)
      7. 6.17.7 Fast Serial Interface (FSI)
        1. 6.17.7.1 FSI Transmitter
          1. 6.17.7.1.1 FSITX Electrical Data and Timing
            1. 6.17.7.1.1.1 FSITX Switching Characteristics
            2. 6.17.7.1.1.2 FSITX Timings
        2. 6.17.7.2 FSI Receiver
          1. 6.17.7.2.1 FSIRX Electrical Data and Timing
            1. 6.17.7.2.1.1 FSIRX Timing Requirements
            2. 6.17.7.2.1.2 FSIRX Switching Characteristics
            3. 6.17.7.2.1.3 FSIRX Timings
        3. 6.17.7.3 FSI SPI Compatibility Mode
          1. 6.17.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.17.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.17.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 6.17.8 Universal Serial Bus (USB)
        1. 6.17.8.1 USB Electrical Data and Timing
          1. 6.17.8.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.17.8.1.2 USB Output Ports DP and DM Switching Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Memory
      1. 7.3.1 Memory Map
        1. 7.3.1.1 Dedicated RAM (Mx RAM)
        2. 7.3.1.2 Local Shared RAM (LSx RAM)
        3. 7.3.1.3 Global Shared RAM (GSx RAM)
        4. 7.3.1.4 Message RAM
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 Peripheral Registers Memory Map
    4. 7.4  Identification
    5. 7.5  Bus Architecture – Peripheral Connectivity
    6. 7.6  C28x Processor
      1. 7.6.1 Floating-Point Unit (FPU)
      2. 7.6.2 Trigonometric Math Unit (TMU)
      3. 7.6.3 VCRC Unit
    7. 7.7  Control Law Accelerator (CLA)
    8. 7.8  Embedded Real-Time Analysis and Diagnostic (ERAD)
    9. 7.9  Direct Memory Access (DMA)
    10. 7.10 Device Boot Modes
      1. 7.10.1 Device Boot Configurations
        1. 7.10.1.1 Configuring Boot Mode Pins
        2. 7.10.1.2 Configuring Boot Mode Table Options
      2. 7.10.2 GPIO Assignments
    11. 7.11 Security
      1. 7.11.1 Securing the Boundary of the Chip
        1. 7.11.1.1 JTAGLOCK
        2. 7.11.1.2 Zero-pin Boot
      2. 7.11.2 Dual-Zone Security
      3. 7.11.3 Disclaimer
    12. 7.12 Watchdog
    13. 7.13 C28x Timers
    14. 7.14 Dual-Clock Comparator (DCC)
      1. 7.14.1 Features
      2. 7.14.2 Mapping of DCCx Clock Source Inputs
    15. 7.15 Configurable Logic Block (CLB)
  9. 8 Reference Design
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Markings
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PNA|80
  • PM|64
  • RSH|56
  • PZ|100
  • PDT|128
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3.1 Analog Signals

Table 5-2 Analog Signals
SIGNAL NAME PIN TYPE DESCRIPTION 128 PDT 100 PZ 80 PNA 64 PM 56 RSH
A0 I ADC-A Input 0 30 23 19 15 13
A1 I ADC-A Input 1 29 22 18 14 12
A2 I ADC-A Input 2 21 17 13 9 7
A3 I ADC-A Input 3 20 18 12 8 6
A4 I ADC-A Input 4 42 36 27 23 21
A5 I ADC-A Input 5 28 35 17 13 11
A6 I ADC-A Input 6 18 14 10 6
A7 I ADC-A Input 7 37 31 23 19 17
A8 I ADC-A Input 8 39 37 24 20 18
A9 I ADC-A Input 9 48 38 28 24 22
A10 I ADC-A Input 10 50 40 29 25 23
A11 I ADC-A Input 11 27 20 16 12 10
A12 I ADC-A Input 12 35 28 22 18 16
A13 I ADC-A Input 13 33, 34 26, 27 21 17 15
A14 I ADC-A Input 14 26 19 15 11 9
A15 I ADC-A Input 15 22 14 10 8
A16 I ADC-A Input 16 2 1 4 2 3
A17 I ADC-A Input 17 60 48 33 27 24
A18 I ADC-A Input 18 61 49 34 28 25
A19 I ADC-A Input 19 62 50 35 29 26
A20 I ADC-A Input 20 63 51 36 30 27
A24 I ADC-A Input 24 64 52 37 31 28
A25 I ADC-A Input 25 67 55 40 34 31
A26 I ADC-A Input 26 24
A27 I ADC-A Input 27 44
A28 I ADC-A Input 28 47
AIO208 I Analog Pin Used For Digital Input 208 23
AIO209 I Analog Pin Used For Digital Input 209 24
AIO210 I Analog Pin Used For Digital Input 210 25
AIO225 I Analog Pin Used For Digital Input 225 42 36 27 23 21
AIO229 I Analog Pin Used For Digital Input 229 18
AIO231 I Analog Pin Used For Digital Input 231 30 23 19 15 13
AIO232 I Analog Pin Used For Digital Input 232 29 22 18 14 12
AIO233 I Analog Pin Used For Digital Input 233 22 14 10 8
AIO234 I Analog Pin Used For Digital Input 234 31, 32 24, 25 20 16 14
AIO235 I Analog Pin Used For Digital Input 235 33, 34 26, 27 21 17 15
AIO237 I Analog Pin Used For Digital Input 237 27 20 16 12 10
AIO238 I Analog Pin Used For Digital Input 238 35 28 22 18 16
AIO239 I Analog Pin Used For Digital Input 239 26 19 15 11 9
AIO240 I Analog Pin Used For Digital Input 240 37
AIO241 I Analog Pin Used For Digital Input 241 39 24 20 18
AIO244 I Analog Pin Used For Digital Input 244 28 21 17 13 11
AIO245 I Analog Pin Used For Digital Input 245 37 31 23 19 17
AIO248 I Analog Pin Used For Digital Input 248 35 29 22 18 16
AIO249 I Analog Pin Used For Digital Input 249 35
AIO251 I Analog Pin Used For Digital Input 251 36 30
AIO252 I Analog Pin Used For Digital Input 252 38 32
B0 I ADC-B Input 0 39 41 24 20 18
B1 I ADC-B Input 1 50 40 29 25 23
B2 I ADC-B Input 2 19 15 11 7
B3 I ADC-B Input 3 20 16 12 8 6
B4 I ADC-B Input 4 49 39 28 24 22
B5 I ADC-B Input 5 38 32
B6 I ADC-B Input 6 21 17 13 9 7
B7 I ADC-B Input 7 29 22 18 14 12
B8 I ADC-B Input 8 42 36 27 23 21
B9 I ADC-B Input 9 22 18 14 10 8
B10 I ADC-B Input 10 27 20 16 12 10
B11 I ADC-B Input 11 36 30
B12 I ADC-B Input 12 28 21 17 13 11
B13 I ADC-B Input 13 33, 34 26, 27 21 17 15
B14 I ADC-B Input 14 26 19 15 11 9
B15 I ADC-B Input 15 30 23 19 15 13
B16 I ADC-B Input 16 2 1 4 2 3
B17 I ADC-B Input 17 60 48 33 27 24
B18 I ADC-B Input 18 61 49 34 28 25
B19 I ADC-B Input 19 62 50 35 29 26
B20 I ADC-B Input 20 63 51 36 30 27
B24 I ADC-B Input 24 65 53 38 32 29
B25 I ADC-B Input 25 68 56 41 35 32
B26 I ADC-B Input 26 25
B27 I ADC-B Input 27 45
B30 I ADC-B Input 30 37 31 23 19 17
C0 I ADC-C Input 0 27 20 16 12 10
C1 I ADC-C Input 1 35 29 22 18 16
C2 I ADC-C Input 2 28 21 17 13 11
C3 I ADC-C Input 3 37 31 23 19 17
C4 I ADC-C Input 4 26 19 15 11 9
C5 I ADC-C Input 5 20 28 12 8 6
C6 I ADC-C Input 6 19 15 11 7
C7 I ADC-C Input 7 22 18 14 10 8
C8 I ADC-C Input 8 49 39 28 24 22
C9 I ADC-C Input 9 21 17 13 9 7
C10 I ADC-C Input 10 50 40 29 25 23
C11 I ADC-C Input 11 39 41 24 20 18
C13 I ADC-C Input 13 33, 34 26, 27 21 17 15
C14 I ADC-C Input 14 42 42 27 23 21
C15 I ADC-C Input 15 30 23 19 15 13
C16 I ADC-C Input 16 2 1 4 2 3
C17 I ADC-C Input 17 60 48 33 27 24
C18 I ADC-C Input 18 61 49 34 28 25
C19 I ADC-C Input 19 62 50 35 29 26
C20 I ADC-C Input 20 63 51 36 30 27
C24 I ADC-C Input 24 66 54 39 33 30
C25 I ADC-C Input 25 23
C26 I ADC-C Input 26 43
C27 I ADC-C Input 27 46
CMP1_DACL I CMPSS-1 Low DAC Output 29 22 18 14 12
CMP1_HN0 I CMPSS-1 High Comparator Negative Input 0 22 14 10 8
CMP1_HN1 I CMPSS-1 High Comparator Negative Input 1 27 20 16 12 10
CMP1_HP0 I CMPSS-1 High Comparator Positive Input 0 21 17 13 9 7
CMP1_HP1 I CMPSS-1 High Comparator Positive Input 1 27 20 16 12 10
CMP1_HP2 I CMPSS-1 High Comparator Positive Input 2 18 14 10 6
CMP1_HP3 I CMPSS-1 High Comparator Positive Input 3 22 14 10 8
CMP1_HP4 I CMPSS-1 High Comparator Positive Input 4 29 22 18 14 12
CMP1_HP5 I CMPSS-1 High Comparator Positive Input 5 38 32
CMP1_LN0 I CMPSS-1 Low Comparator Negative Input 0 22 14 10 8
CMP1_LN1 I CMPSS-1 Low Comparator Negative Input 1 27 20 16 12 10
CMP1_LP0 I CMPSS-1 Low Comparator Positive Input 0 21 17 13 9 7
CMP1_LP1 I CMPSS-1 Low Comparator Positive Input 1 27 20 16 12 10
CMP1_LP2 I CMPSS-1 Low Comparator Positive Input 2 18 14 10 6
CMP1_LP3 I CMPSS-1 Low Comparator Positive Input 3 22 14 10 8
CMP1_LP4 I CMPSS-1 Low Comparator Positive Input 4 29 22 18 14 12
CMP1_LP5 I CMPSS-1 Low Comparator Positive Input 5 38 32
CMP2_HN0 I CMPSS-2 High Comparator Negative Input 0 50 40 29 25 23
CMP2_HN1 I CMPSS-2 High Comparator Negative Input 1 35 28 22 18 16
CMP2_HP0 I CMPSS-2 High Comparator Positive Input 0 42 36 27 23 21
CMP2_HP1 I CMPSS-2 High Comparator Positive Input 1 35 28 22 18 16
CMP2_HP2 I CMPSS-2 High Comparator Positive Input 2 48 38 28 24 22
CMP2_HP3 I CMPSS-2 High Comparator Positive Input 3 50 40, 41 29 25 23
CMP2_HP5 I CMPSS-2 High Comparator Positive Input 5 28 35 17 13 11
CMP2_LN0 I CMPSS-2 Low Comparator Negative Input 0 50 40 29 25 23
CMP2_LN1 I CMPSS-2 Low Comparator Negative Input 1 35 28 22 18 16
CMP2_LP0 I CMPSS-2 Low Comparator Positive Input 0 42 36 27 23 21
CMP2_LP1 I CMPSS-2 Low Comparator Positive Input 1 35 28 22 18 16
CMP2_LP2 I CMPSS-2 Low Comparator Positive Input 2 48 38 28 24 22
CMP2_LP3 I CMPSS-2 Low Comparator Positive Input 3 50 40, 41 29 25 23
CMP2_LP5 I CMPSS-2 Low Comparator Positive Input 5 28 35 17 13 11
CMP3_HN0 I CMPSS-3 High Comparator Negative Input 0 20 16 12 8 6
CMP3_HN1 I CMPSS-3 High Comparator Negative Input 1 28 21 17 13 11
CMP3_HP0 I CMPSS-3 High Comparator Positive Input 0 19 15 11 7
CMP3_HP1 I CMPSS-3 High Comparator Positive Input 1 28 21 17 13 11
CMP3_HP2 I CMPSS-3 High Comparator Positive Input 2 30 23 19 15 13
CMP3_HP3 I CMPSS-3 High Comparator Positive Input 3 20 16 12 8 6
CMP3_HP4 I CMPSS-3 High Comparator Positive Input 4 26 19 15 11 9
CMP3_HP5 I CMPSS-3 High Comparator Positive Input 5 20 18 12 8 6
CMP3_LN0 I CMPSS-3 Low Comparator Negative Input 0 20 16 12 8 6
CMP3_LN1 I CMPSS-3 Low Comparator Negative Input 1 28 21 17 13 11
CMP3_LP0 I CMPSS-3 Low Comparator Positive Input 0 19 15 11 7
CMP3_LP1 I CMPSS-3 Low Comparator Positive Input 1 28 21 17 13 11
CMP3_LP2 I CMPSS-3 Low Comparator Positive Input 2 30 23 19 15 13
CMP3_LP3 I CMPSS-3 Low Comparator Positive Input 3 20 16 12 8 6
CMP3_LP4 I CMPSS-3 Low Comparator Positive Input 4 26 19 15 11 9
CMP3_LP5 I CMPSS-3 Low Comparator Positive Input 5 20 18 12 8 6
CMP4_HN0 I CMPSS-4 High Comparator Negative Input 0 42 42 27 23 21
CMP4_HN1 I CMPSS-4 High Comparator Negative Input 1 37 31 23 19 17
CMP4_HP0 I CMPSS-4 High Comparator Positive Input 0 49 39 28 24 22
CMP4_HP1 I CMPSS-4 High Comparator Positive Input 1 37 31 23 19 17
CMP4_HP2 I CMPSS-4 High Comparator Positive Input 2 35 29 22 18 16
CMP4_HP3 I CMPSS-4 High Comparator Positive Input 3 42 42 27 23 21
CMP4_HP4 I CMPSS-4 High Comparator Positive Input 4 39 37 24 20 18
CMP4_HP5 I CMPSS-4 High Comparator Positive Input 5 36 30
CMP4_LN0 I CMPSS-4 Low Comparator Negative Input 0 42 42 27 23 21
CMP4_LN1 I CMPSS-4 Low Comparator Negative Input 1 37 31 23 19 17
CMP4_LP0 I CMPSS-4 Low Comparator Positive Input 0 49 39 28 24 22
CMP4_LP1 I CMPSS-4 Low Comparator Positive Input 1 37 31 23 19 17
CMP4_LP2 I CMPSS-4 Low Comparator Positive Input 2 35 29 22 18 16
CMP4_LP3 I CMPSS-4 Low Comparator Positive Input 3 42 42 27 23 21
CMP4_LP4 I CMPSS-4 Low Comparator Positive Input 4 39 37 24 20 18
CMP4_LP5 I CMPSS-4 Low Comparator Positive Input 5 36 30
D0 I ADC-D Input 0 64 52 37 31 28
D1 I ADC-D Input 1 65 53 38 32 29
D2 I ADC-D Input 2 66 54 39 33 30
D3 I ADC-D Input 3 67 55 40 34 31
D4 I ADC-D Input 4 68 56 41 35 32
D5 I ADC-D Input 5 23
D6 I ADC-D Input 6 24
D7 I ADC-D Input 7 25
D8 I ADC-D Input 8 43
D9 I ADC-D Input 9 44
D10 I ADC-D Input 10 45
D11 I ADC-D Input 11 29 22 18 14 12
D12 I ADC-D Input 12 37 31 23 19 17
D13 I ADC-D Input 13 33, 34 26, 27 21 17 15
D14 I ADC-D Input 14 18 14 10 6
D15 I ADC-D Input 15 38 32
D16 I ADC-D Input 16 36 30
D18 I ADC-D Input 18 46
D19 I ADC-D Input 19 47
D20 I ADC-D Input 20 31, 32 24, 25 20 16 14
DACA_OUT O Buffered DAC-A Output. 30 23 19 15 13
E0 I ADC-E Input 0 64 52 37 31 28
E1 I ADC-E Input 1 65 53 38 32 29
E2 I ADC-E Input 2 66 54 39 33 30
E3 I ADC-E Input 3 67 55 40 34 31
E4 I ADC-E Input 4 68 56 41 35 32
E5 I ADC-E Input 5 23
E6 I ADC-E Input 6 24
E7 I ADC-E Input 7 25
E8 I ADC-E Input 8 43
E9 I ADC-E Input 9 44
E10 I ADC-E Input 10 45
E11 I ADC-E Input 11 35 29 22 18 16
E12 I ADC-E Input 12 19 15 11 7
E13 I ADC-E Input 13 33, 34 26, 27 21 17 15
E14 I ADC-E Input 14 18 14 10 6
E15 I ADC-E Input 15 38 32
E16 I ADC-E Input 16 36 30
E18 I ADC-E Input 18 46
E19 I ADC-E Input 19 47
E20 I ADC-E Input 20 31, 32 24, 25 20 16 14
E30 I ADC-E Input 30 37 31 23 19 17
PGA1_INM I PGA-1 Minus 22 18 14 10 8
PGA1_INP I PGA-1 Plus 21 17 13 9 7
PGA1_OUT O PGA-1 Output 26 19 15 11 9
PGA2_INM I PGA-2 Minus 28 21 17 13 11
PGA2_INP I PGA-2 Plus 20 16 12 8 6
PGA2_OUT O PGA-2 Output 27 20 16 12 10
PGA3_INM I PGA-3 Minus 36 30 23 19 17
PGA3_INP I PGA-3 Plus 35 29 22 18 16
PGA3_OUT O PGA-3 Output 38 32 24 20 18
VREFHI(1) I ADC High Reference. This can be sourced from either the internal voltage reference or from an external voltage reference. In either case a 2.2-µF capacitor between VREFHI and VREFLO must be placed on this pin. This capacitor should be placed as close to the device as possible. If all ADCs use the internal connection to VDDA to supply the high reference, then the ADC channels D20 and E20 can be sampled on the shared analog pin and the capacitor is not needed. 31, 32 24, 25 20 16 14
VREFLO(2) I ADC Low Reference If all ADCs use the internal connection to VSSA to supply the low reference, then the ADC channels A13/B13/C13/D13/E13 can be sampled on the shared analog pin. 33, 34 26, 27 21 17 15
(1) On the 128-PDT package, VREFHI is assigned to pins 31 and 32; these pins should be tied together at the PCB level. On the 100-PZ package, VREFHI is assigned to pins 24 and 25; these pins should be tied together at the PCB level.
(2) On the 128-PDT package, VREFLO is assigned to pins 33 and 34; these pins should be tied together at the PCB level. On the 100-PZ package, VREFLO is assigned to pins 26 and 27; these pins should be tied together at the PCB level.