SPNS253A May 2018 – September 2019 TMS570LC4357-EP
PRODUCTION DATA.
MEMORY | RAM
GROUP |
TEST CLOCK | RGS | RDS | MEM
TYPE |
NO.
BANKS |
TEST PATTERN
(ALGORITHM) |
|||
---|---|---|---|---|---|---|---|---|---|---|
TRIPLE READ
SLOW READ |
TRIPLE READ
FAST READ |
March 13N(1)
TWO PORT (cycles) |
March 13N(1)
SINGLE PORT (cycles) |
|||||||
ALGO MASK 0x1 | ALGO MASK 0x2 | ALGO MASK 0x4 | ALGO MASK 0x8 | |||||||
PBIST_ROM | 1 | GCM_PBIST_ROM | 1 | 1 | ROM | 1 | 24578 | 8194 | ||
STC1_1_ROM_R5 | 2 | GCM_PBIST_ROM | 14 | 1 | ROM | 1 | 49154 | 16386 | ||
STC1_2_ROM_R5 | 3 | GCM_PBIST_ROM | 14 | 2 | ROM | 1 | 49154 | 16386 | ||
STC2_ROM_NHET | 4 | GCM_PBIST_ROM | 15 | 1 | ROM | 1 | 46082 | 15362 | ||
AWM1 | 5 | GCM_VCLKP | 2 | 1 | 2P | 1 | 4210 | |||
DCAN1 | 6 | GCM_VCLKP | 3 | 1..6 | 2P | 2 | 25260 | |||
DCAN2 | 7 | GCM_VCLKP | 4 | 1..6 | 2P | 2 | 25260 | |||
DMA | 8 | GCM_HCLK | 5 | 1..6 | 2P | 2 | 37740 | |||
HTU1 | 9 | GCM_VCLK2 | 6 | 1..6 | 2P | 2 | 6540 | |||
MIBSPI1 | 10 | GCM_VCLKP | 8 | 1..4 | 2P | 2 | 66760 | |||
MIBSPI2 | 11 | GCM_VCLKP | 9 | 1..4 | 2P | 2 | 33480 | |||
MIBSPI3 | 12 | GCM_VCLKP | 10 | 1..4 | 2P | 2 | 33480 | |||
NHET1 | 13 | GCM_VCLK2 | 11 | 1..12 | 2P | 4 | 50520 | |||
VIM | 14 | GCM_VCLK | 12 | 1..2 | 2P | 1 | 16740 | |||
Reserved | 15 | - | - | - | - | - | - | |||
RTP | 16 | GCM_HCLK | 16 | 1..12 | 2P | 4 | 50520 | |||
ATB(2) | 17 | GCM_GCLK1 | 17 | 1..16 | 2P | 8 | 133920 | |||
AWM2 | 18 | GCM_VCLKP | 18 | 1 | 2P | 1 | 4210 | |||
DCAN3 | 19 | GCM_VCLKP | 19 | 1..6 | 2P | 2 | 25260 | |||
DCAN4 | 20 | GCM_VCLKP | 20 | 1..6 | 2P | 2 | 25260 | |||
HTU2 | 21 | GCM_VCLK2 | 21 | 1..6 | 2P | 2 | 6540 | |||
MIBSPI4 | 22 | GCM_VCLKP | 22 | 1..4 | 2P | 2 | 33480 | |||
MIBSPI5 | 23 | GCM_VCLKP | 23 | 1..4 | 2P | 2 | 33480 | |||
NHET2 | 24 | GCM_VCLK2 | 24 | 1..12 | 2P | 4 | 50520 | |||
FTU | 25 | GCM_VCLKP | 25 | 1 | 2P | 1 | 8370 | |||
FRAY_INBUF_OUTBUF | 26 | GCM_VCLKP | 26 | 1..8 | 2P | 4 | 33680 | |||
CPGMAC_STATE_RXADDR | 27 | GCM_VCLK3 | 27 | 1..3 | 2P | 2 | 6390 | |||
CPGMAC_STAT_FIFO | 28 | GCM_VCLK3 | 27 | 4..6 | 2P | 3 | 8730 | |||
L2RAMW | 29 | GCM_HCLK | 7 | 1 | SP | 4 | 532580 | |||
6 | SP | 4 | ||||||||
L2RAMW | 30 | GCM_HCLK | 32 | 1 | SP | 4 | 1597740 | |||
6 | SP | 4 | ||||||||
11 | SP | 4 | ||||||||
16 | SP | 4 | ||||||||
21 | SP | 4 | ||||||||
26 | SP | 4 | ||||||||
R5_ICACHE | 31 | GCM_GCLK1 | 40 | 1 | SP | 4 | 166600 | |||
6 | SP | 4 | ||||||||
11 | SP | 4 | ||||||||
16 | SP | 4 | ||||||||
R5_DCACHE | 32 | GCM_GCLK1 | 41 | 1 | SP | 4 | 299820 | |||
6 | SP | 4 | ||||||||
11 | SP | 4 | ||||||||
16 | SP | 4 | ||||||||
21 | SP | 4 | ||||||||
26 | SP | 4 | ||||||||
Reserved | 33 | GCM_GCLK2 | 43 | 1 | SP | 4 | 166600 | |||
6 | SP | 4 | ||||||||
11 | SP | 4 | ||||||||
16 | SP | 4 | ||||||||
Reserved | 34 | GCM_GCLK2 | 44 | 1 | SP | 4 | 299820 | |||
6 | SP | 4 | ||||||||
11 | SP | 4 | ||||||||
16 | SP | 4 | ||||||||
21 | SP | 4 | ||||||||
26 | SP | 4 | ||||||||
FRAY_TRBUF_MSGRAM | 35 | GCM_VCLKP | 26 | 9..11 | SP | 3 | 149910 | |||
CPGMAC_CPPI | 36 | GCM_VCLK3 | 27 | 7 | SP | 1 | 133170 | |||
R5_DCACHE_Dirty | 37 | GCM_GCLK1 | 42 | 2 | SP | 1 | 16690 | |||
Reserved | 38 | - | - | - | - | - | - |
Several memory testing algorithms are stored in the PBIST ROM. However, TI only recommends the March13N algorithm for application testing of RAM.
The PBIST ROM clock frequency is limited to the maximum frequency of 82.5 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.