Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET module provides this capability through the "Pin Disable" input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated.
For more details on the "N2HET Pin Disable" feature, see the device-specific Technical Reference Manual listed in Section 8.2.1.
GIOA and EQEPERR are connected to the "Pin Disable" input for N2HET. In the case of GIOA connection, this connection is made from the output of the input buffer. In the case of EQEPERR, the EQEPERR output signal is asserted in the event of a phase error. This signal is inverted and double-synchronized to VCLK2 for input into the N2HET PIN_nDISABLE port.
The PIN_nDISABLE port input source is selectable between the GIOA and EQEPERR sources. This is achieved through the PINMMR9[1:0] bits.