6.4.1 Summary of ARM Cortex-R4 CPU Features
The features of the ARM Cortex-R4 CPU include:
- An integer unit with integral Embedded ICE-RT logic.
- High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced eXtensible Interfaces (AXI) for Level two (L2) master and slave interfaces.
- Dynamic branch prediction with a global history buffer, and a 4-entry return stack
- Low interrupt latency.
- Nonmaskable interrupt.
- A Harvard Level one (L1) memory system with:
- Tightly Coupled Memory (TCM) interfaces with support for error correction or parity checking memories
- ARMv7-R architecture Memory Protection Unit (MPU) with 8 regions
- Dual core logic for fault detection in safety-critical applications.
- An L2 memory interface:
- Single 64-bit master AXI interface
- 64-bit slave AXI interface to TCM RAM blocks
- A debug interface to a CoreSight Debug Access Port (DAP).
- Six Hardware Breakpoints
- Two Watchpoints
- A Perfomance Monitoring Unit (PMU)
- A Vectored Interrupt Controller (VIC) port.
For more information on the ARM Cortex-R4 CPU, see www.arm.com.