The TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required. There are no registers which need to be programmed for RAM wait states.
The TCM flash can support zero address and data wait states up to a CPU speed of 45 MHz in nonpipelined mode.The flash supports a maximum CPU clock speed of 80 MHz in pipelined mode with no address wait states and one data wait state.
The proper wait states should be set in the register fields Address Setup Wait State Enable (ASWSTEN 0xFFF87000), Random Wait states (RWAIT 0xFFF87000[11:8]), and Emulation Wait states (EWAIT 0xFFF872B8[19:16]) as shown in Figure 5-1.
The flash wrapper defaults to nonpipelined mode with address wait states disabled, ASWSTEN=0; the main memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1.