SCDS445E May   2022  – September 2024 TMUX4051 , TMUX4052 , TMUX4053

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information: TMUX405x
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Propagation Delay
    8. 7.8  Charge Injection
    9. 7.9  Off Isolation
    10. 7.10 Crosstalk
    11. 7.11 Bandwidth
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Device Functional Modes
      5. 8.3.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
    5. 9.5 Application Curves
    6. 9.6 Power Supply Recommendations
    7. 9.7 Layout
      1. 9.7.1 Layout Guidelines
      2. 9.7.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TMUX4051 TMUX4052 TMUX4053 TMUX4051 PW Package,16-Pin TSSOP(Top View)Figure 5-1 TMUX4051 PW Package,16-Pin TSSOP(Top View)
TMUX4051 TMUX4052 TMUX4053 TMUX4051 DYY Package,16-Pin SOT-23-THIN(Top View)Figure 5-2 TMUX4051 DYY Package,16-Pin SOT-23-THIN(Top View)
TMUX4051 TMUX4052 TMUX4053 TMUX4051 BQB Package,16-Pin WQFN(Top View) Figure 5-3 TMUX4051 BQB Package,16-Pin WQFN(Top View)
Table 5-1 Pin Functions TMUX4051
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S4 1 I/O Source pin 4. Signal path can be an input or output.
S6 2 I/O Source pin 6. Signal path can be an input or output.
D 3 I/O Drain pin (common). Signal path can be an input or output.
S7 4 I/O Source pin 7. Signal path can be an input or output.
S5 5 I/O Source pin 5. Signal path can be an input or output.
EN 6 I Active low logic enable. When this pin is high, all switches are turned off. Table 8-1 lists how the A[2:0] address inputs determine which switch is turned on when this pin is low.
VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
GND 8 P Ground (0V) reference
A2 9 I Address line 2. Table 8-1 provides information about how A2 controls the switch configuration.
A1 10 I Address line 1. Table 8-1 provides information about how A1 controls the switch configuration.
A0 11 I Address line 0. Table 8-1 provides information about how A0 controls the switch configuration.
S3 12 I/O Source pin 3. Signal path can be an input or output.
S0 13 I/O Source pin 0. Signal path can be an input or output.
S1 14 I/O Source pin 1. Signal path can be an input or output.
S2 15 I/O Source pin 2. Signal path can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
Thermal pad — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 8.3.4.
TMUX4051 TMUX4052 TMUX4053 TMUX4052 PW Package,16-Pin TSSOP(Top View)Figure 5-4 TMUX4052 PW Package,16-Pin TSSOP(Top View)
TMUX4051 TMUX4052 TMUX4053 TMUX4052 DYY Package,16-Pin SOT-23-THIN(Top View)Figure 5-5 TMUX4052 DYY Package,16-Pin SOT-23-THIN(Top View)
TMUX4051 TMUX4052 TMUX4053 TMUX4052 BQB Package,16-Pin WQFN(Top View) Figure 5-6 TMUX4052 BQB Package,16-Pin WQFN(Top View)
Table 5-2 Pin Functions TMUX4052
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S0B 1 I/O Source pin 0 of mux B. Can be an input or output.
S2B 2 I/O Source pin 2 of mux B. Can be an input or output.
DB 3 I/O Drain pin (common) of mux B. Can be an input or output.
S3B 4 I/O Source pin 3 of mux B. Can be an input or output.
S1B 5 I/O Source pin 1 of mux B. Can be an input or output.
EN 6 I Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the A[1:0] address inputs determine which switch is turned on.
VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
GND 8 P Ground (0V) reference
A1 9 I Address line 1. Table 8-2 provides information about how A1 controls the switch configuration.
A0 10 I Address line 0. Table 8-2 provides information about how A0 controls the switch configuration.
S3A 11 I/O Source pin 3 of mux A. Can be an input or output.
S0A 12 I/O Source pin 0 of mux A. Can be an input or output.
DA 13 I/O Drain pin (common) of mux A. Can be an input or output.
S1A 14 I/O Source pin 1 of mux A. Can be an input or output.
S2A 15 I/O Source pin 2 of mux A. Can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
Thermal pad — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 8.3.4 .
TMUX4051 TMUX4052 TMUX4053 TMUX4053 PW Package,16-Pin TSSOP(Top View)Figure 5-7 TMUX4053 PW Package,16-Pin TSSOP(Top View)
TMUX4051 TMUX4052 TMUX4053 TMUX4053 DYY Package,16-Pin SOT-23-THIN(Top View)Figure 5-8 TMUX4053 DYY Package,16-Pin SOT-23-THIN(Top View)
TMUX4051 TMUX4052 TMUX4053 TMUX4053 BQB Package,16-Pin WQFN(Top View) Figure 5-9 TMUX4053 BQB Package,16-Pin WQFN(Top View)
Table 5-3 Pin Functions TMUX4053
PIN TYPE(1) DESCRIPTION(2)
NAME NO.
S2B 1 I/O Source pin B of switch 2. Can be an input or output.
S2A 2 I/O Source pin A of switch 2. Can be an input or output.
S3B 3 I/O Source pin B of switch 3. Can be an input or output.
D3 4 I/O Drain pin (common) of switch 3. Can be an input or output.
S3A 5 I/O Source pin A of switch 3. Can be an input or output.
EN 6 I Active low logic enable. When this pin is high, all switches are turned off. When this pin is low, the SEL[x] logic control inputs determine which switch is turned on.
VSS 7 P Negative power supply. This pin is the most negative power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
GND 8 P Ground (0V) reference
SEL3 9 I Logic control select pin 3. Table 8-2 provides controls switch 3 configuration.
SEL2 10 I Logic control select pin 2. Table 8-2 provides controls switch 2 configuration.
SEL1 11 I Logic control select pin 1. Table 8-2 provides controls switch 1 configuration.
S1A 12 I/O Source pin A of switch 1. Can be an input or output.
S1B 13 I/O Source pin B of switch 1. Can be an input or output.
D1 14 I/O Drain pin (common) of switch 1. Can be an input or output.
D2 15 I/O Drain pin (common) of switch 2. Can be an input or output.
VDD 16 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
Thermal pad — The thermal pad is not connected internally. It is recommended that the pad be left floating or tied to GND.
(1) I = input, O = output, I/O = input and output, P = power.
(2) For what to do with unused pins, refer to Section 8.3.4.