SLVSIV4A September 2025 – November 2025 TMUXHS221F
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Power | ||||||
| ICC-ACTIVE | Active supply current | OEn = 0V SEL= 0V, 1.2V or VCC 0V < VI/O < 3.6V |
23 | 62 | µA | |
| ICC-OVP | Supply current during OVP condition | OEn = 0V SEL = 0V, 1.2V or VCC VI/O > VPOS_THLD |
24 | 55 | μA | |
| ICC_PD_OVP | Standby powered down supply current | OEn = 1.2V, 1.8V, or VCC SEL = 0V, 1.2V, 1.8V, or VCC |
5 | 15 | µA | |
| ICC_PD | Standby powered down supply current | OEn = 1.2V, 1.8V, or VCC SEL = 0V, 1.2V, 1.8V, or VCC |
2 | 8 | µA | |
| DC Characteristics | ||||||
| RON | ON-state resistance | VI/O = 0.4V ISINK = 8mA VCC = 1.62V - 5.5V |
5.6 | 13 | Ω | |
| ΔRON | ON-state resistance match between channels | VI/O = 0.4V VCC=1.62V-5.5V ISINK = 8mA |
0.173 | 0.349 | Ω | |
| RON (FLAT) | ON-state resistance flatness | VI/O = 0V to 0.4V VCC=1.62 ISINK = 8mA |
0.09 | 0.36 | Ω | |
| RON (FLAT) | ON-state resistance flatness | VI/O = 0V to 0.4V VCC=2.3V-5.5V ISINK = 8mA |
0.055 | 0.36 | Ω | |
| IOFF_0V | I/O pin OFF leakage current when VCC = 0V | OEn = H VD± = 0V or 3.6V VCC = 0V VD1±or VD2± = 3.6V |
–12.5 | 0.9 | 15.5 | µA |
| IOFF | I/O pin OFF leakage current | OEn = H VD± = 0V or 3.6V VCC = 1.62V to 5.5V VD1±or VD2± = 3.6V |
–2.73 | 0.1 | 2.73 | µA |
| IOFF-28V | D1±, D2± pin OFF leakage current during OVP scenario on D± | OEn = H VD± = 28V VCC = 1.62V to 5.5V VD1± or VD2± = 0V |
-0.5 | 0.5 | µA | |
| IOFF-28V-DPN | D± pin OFF leakage current during OVP scenario | OEn = H VD± = VOVP_THREDHOLD to 28V VCC = 1.62V to 5.5V VD1± or VD2± = 0V |
220 | 626 | 807 | µA |
| ION | ON leakage current | VD± = 3.6V VD1± and VD2± = High-Z |
–5.5 | 0.25 | 7.5 | µA |
| Digital Characteristics | ||||||
| VIH | Input logic high | SEL, OEn | 0.77 | V | ||
| VIL | Input logic low | SEL, OEn | 0.39 | V | ||
| IIH | Input high leakage current | SEL, OEn = 1.2V, 1.8V, or VCC | –1 | 0.35 | 5 | μA |
| IIL | Input low leakage current | SEL, OEn = 0V | –1 | ±0.002 | 5 | μA |
| CI | Digital input capacitance | SEL = 0V, 1.2V, 1.8V, or VCC f = 1MHz |
3 | pF | ||
| Protection | ||||||
| VOVP_TH | OVP positive threshold (D± rising) | 4.5 | 5.1 | 5.7 | V | |
| VOVP_HYST | OVP threshold hysteresis | 110 | 250 | 440 | mV | |
| VCLAMP_V | Maximum voltage to appear on D1± and D2± pins during OVP scenario | VD± = 0V to 28V VCC=1.62V-5.5V tRISE (10% to 90%) = 100ns RL = Open OEn= 0V |
7.24 | 7.67 | V | |
| VD± = 0V to 28V VCC=1.62V-5.5V tRISE (10% to 90%) = 100ns RL = 50Ω Switch on or off OEn = 0V |
6.8 | 7.3 | V | |||
| tCLAMP | Maximum OVP transient duration above 5V | VD± = 0V to 28V VCC=1.62 tRISE (10% to 90%) = 100ns RL = Open OEn= 0V |
54 | 130 | ns | |
| tCLAMP | Maximum OVP transient duration above 5V | VD± = 0V to 28V VCC=2.3V-5.5V tRISE (10% to 90%) = 100ns RL = Open OEn= 0V |
54 | 84 | ns | |
| VD± = 0V to 28V tRISE (10% to 90%) = 100ns RL = 50Ω Switch on or off OEn = 0V |
39 | 56 | ns | |||