SLASF51 February   2024 TMUXHS4446

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 High-Speed Performance Parameters
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Timing Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High-Speed Differential Signal Switching
      2. 6.3.2 Low-Speed SBU Signal Switching
      3. 6.3.3 GPIO and I2C Control Modes
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application: USB-C with DP Alternate Mode - Source
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 I2C Timing Characteristics

For pins SDA, SCL and A[1:0] when the device is in I2C control mode (MODE0 = H)
PARAMETER MIN TYP MAX UNIT
fSCL Clock frequency on SCL pin 400 kHz
tCH Clock HIGH time on SCL pin 0.6 µs
tCL Clock LOW time on SCL pin 1.3 µs
tSETSTA Start or repeated start condition setup time 0.6 µs
tHSTA Start or repeated start condition hold time 0.6 µs
tSETDAT Data setup time 100 ns
tHDAT Data hold time 0 0.9 µs
tr Input rise time 20 + 0.1 Cb (1) 300 ns
tf Input fall time 20 + 0.1 Cb (1) 300 ns
tSETSTO Stop condition setup time 0.6 us
tSP Pulse width of spikes which must be suppressed by the input filter 50 ns
tVD-DAT Data valid time 0.9 µs
tVD-ACK Data valid acknowledge time 0.9 µs
(1) Cb = total bus capacitance of one bus line in pF