SNAS806 September   2020 TPL1401

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast Mode Plus
    9. 6.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 6.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Potentiometer (Digipot) Architecture
        1. 7.3.1.1 Reference Selection and Digipot Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 Digipot Update
      3. 7.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check
          1. 7.3.3.1.1 NVM_CRC_ALARM_USER Bit
          2. 7.3.3.1.2 NVM_CRC_ALARM_INTERNAL Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 Software Reset
      6. 7.3.6 Device Lock Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
      3. 7.5.3 Address Byte
      4. 7.5.4 Command Byte
      5. 7.5.5 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h)
      2. 7.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
      3. 7.6.3 PROTECT Register (address = D3h) (reset = 0008h)
      4. 7.6.4 DPOT_POSITION Register (address = 21h) (reset = 0000h)
      5. 7.6.5 USER_BYTE1 Register (address = 25h) (reset = 0000h)
      6. 7.6.6 USER_BYTE2 Register (address = 26h) (reset = 0000h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.3 PROTECT Register (address = D3h) (reset = 0008h)

Figure 7-7 PROTECT Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEVICE_UNLOCK_CODE X DEVICE_
CONFIG_
RESET		 RESERVED NVM_
RELOAD		 NVM_
PROG		 SW_RESET
W-0h X W-0h R-0h W-0h W-0h W-8h
Table 7-14 PROTECT Register Field Descriptions
Bit Field Type Reset Description
15 - 12 DEVICE_UNLOCK_CODE W 0000 Write 0101 to unlock the device to bypass DEVICE_LOCK bit.
11 - 10 X X 0h Don't care
9 DEVICE_CONFIG_RESET W 0 0: Device configuration reset not initiated
1: Device configuration reset initiated. All registers loaded with factory reset values.
8 - 6 RESERVED R 000 Always write 000b
5 NVM_RELOAD W 0 0: NVM reload not initiated
1: NVM reload initiated, applicable digipot registers loaded with corresponding NVM. NVM_BUSY bit set to 1 while this operation is in progress. This bit is self-resetting.
4 NVM_PROG W 0 0: NVM write not initiated
1: NVM write initiated, NVM corresponding to applicable digipot registers loaded with existing register settings. NVM_BUSY bit set to 1 while this operation is in progress. This bit is self-resetting.
3 - 0 SW_RESET W 1000 1000: Software reset not initiated
1010: Software reset initiated, digipot registers loaded with corresponding NVMs, all other registers loaded with default settings.