SNAS806 September   2020 TPL1401

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast Mode Plus
    9. 6.9  Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    10. 6.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital Potentiometer (Digipot) Architecture
        1. 7.3.1.1 Reference Selection and Digipot Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 Digipot Update
      3. 7.3.3 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check
          1. 7.3.3.1.1 NVM_CRC_ALARM_USER Bit
          2. 7.3.3.1.2 NVM_CRC_ALARM_INTERNAL Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 Software Reset
      6. 7.3.6 Device Lock Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
      3. 7.5.3 Address Byte
      4. 7.5.4 Command Byte
      5. 7.5.5 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h)
      2. 7.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)
      3. 7.6.3 PROTECT Register (address = D3h) (reset = 0008h)
      4. 7.6.4 DPOT_POSITION Register (address = 21h) (reset = 0000h)
      5. 7.6.5 USER_BYTE1 Register (address = 25h) (reset = 0000h)
      6. 7.6.6 USER_BYTE2 Register (address = 26h) (reset = 0000h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Requirements: I2C Fast Mode

all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V,  –40°C ≤ TA ≤ +125°C, and
1.8 V ≤ Vpull-up ≤ VDD (unless otherwise specified)
MIN NOM MAX UNIT
fSCLK SCL frequency 0.4 MHz
tBUF Bus free time between stop and start conditions 1.3 µs
tHDSTA Hold time after repeated start 0.6 µs
tSUSTA Repeated start setup time 0.6 µs
tSUSTO Stop condition setup time 0.6 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 100 ns
tLOW SCL clock low period 1300 ns
tHIGH SCL clock high period 600 ns
tF Clock and data fall time 300 ns
tR Clock and data rise time 300 ns