SLUSD53G March   2018  – August 2020 TPS23880

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Power-on Fault Register
        30. 9.6.2.30 PORT RE-MAPPING Register
        31. 9.6.2.31 Channels 1 and 2 Multi Bit Priority Register
        32. 9.6.2.32 Channels 3 and 4 Multi Bit Priority Register
        33. 9.6.2.33 4-Pair Wired and Port Power Allocation Register
        34. 9.6.2.34 4-Pair Police Ch-1 and 2 Configuration Register
        35. 9.6.2.35 4-Pair Police Ch-3 and 4 Configuration Register
        36. 9.6.2.36 TEMPERATURE Register
        37. 9.6.2.37 4-Pair Fault Configuration Register
        38. 9.6.2.38 INPUT VOLTAGE Register
        39. 9.6.2.39 CHANNEL 1 CURRENT Register
        40. 9.6.2.40 CHANNEL 2 CURRENT Register
        41. 9.6.2.41 CHANNEL 3 CURRENT Register
        42. 9.6.2.42 CHANNEL 4 CURRENT Register
        43. 9.6.2.43 CHANNEL 1 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 2 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 3 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 4 VOLTAGE Register
        47. 9.6.2.47 2x FOLDBACK SELECTION Register
        48.       95
        49. 9.6.2.48 FIRMWARE REVISION Register
        50. 9.6.2.49 I2C WATCHDOG Register
        51. 9.6.2.50 DEVICE ID Register
        52. 9.6.2.51 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.54 CHANNEL 4 DETECT RESISTANCE Register
        56. 9.6.2.55 CHANNEL 1 ASSIGNED CLASS Register
        57. 9.6.2.56 CHANNEL 2 ASSIGNED CLASS Register
        58. 9.6.2.57 CHANNEL 3 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 4 ASSIGNED CLASS Register
        60. 9.6.2.59 AUTO CLASS CONTROL Register
        61. 9.6.2.60 CHANNEL 1 AUTO CLASS POWER Register
        62. 9.6.2.61 CHANNEL 2 AUTO CLASS POWER Register
        63. 9.6.2.62 CHANNEL 3 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 4 AUTO CLASS POWER Register
        65. 9.6.2.64 ALTERNATIVE FOLDBACK Register
        66. 9.6.2.65 SRAM CONTROL Register
          1. 9.6.2.65.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.65.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.65.3 116
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.2.7 SUPPLY and FAULT EVENT Register

COMMAND = 0Ah with 1 Data Byte, Read only

COMMAND = 0Bh with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear on Read command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Figure 9-14 SUPPLY and FAULT EVENT Register Format
7 6 5 4 3 2 1 0
TSD VDUV VDWRN VPUV PCUT34 PCUT12 OSSE RAMFLT
R R R R R R R R
CR CR CR CR CR CR CR CR
LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset
Table 9-12 SUPPLY and FAULT EVENT Register Field Descriptions
Bit Field Type POR/RST Description
7 TSD R or CR 0 / P Indicates that a thermal shutdown occurred. When there is thermal shutdown, all channels are turned off and are put in OFF mode. The TPS23880 internal circuitry continues to operate however, including the ADCs. Note that at as soon as the internal temperature has decreased below the low threshold, the channels can be turned back ON regardless of the status of the TSD bit.

1 = Thermal shutdown occurred

0 = No thermal shutdown occurred
6 VDUV R or CR 1 / P Indicates that a VDD UVLO occurred.

1 = VDD UVLO occurred

0 = No VDD UVLO occurred
5 VDWRN R or CR 1 / P Indicates that the VDD has fallen under the UVLO warning threshold.

1 = VDD UV Warning occurred

0 = No VDD UV warning occurred
4 VPUV R or CR 1 / P Indicates that a VPWR undervoltage occurred.

1 = VPWR undervoltage occurred

0 = No VPWR undervoltage occurred
3 PCUT34 R or CR 0 / 0 Indicates that a 4-Pair Summed PCUT fault occurred on channels 3 and 4.

1 = 4-Pair Summed PCUT fault occurred on channels 3 and 4

0 = No Summed PCUT fault occurred
2 PCUT12 R or CR 0 / 0 Indicates that a 4-Pair Summed PCUT fault occurred on channels 1 and 2.

1 = 4-Pair Summed PCUT fault occurred on channels 1 and 2

0 = No Summed PCUT fault occurred
1 OSSE R or CR 0 / 0 Indicates that an OSS Event occurred

1 = one or more channels with a group of 4 were disabled due to the assertion of the OSS pin or provided 3-bit OSS code

0 = No OSS events occurred
0 RAMFLT R or CR 0 / 0 Indicates that a SRAM fault has occurred

1 = SRAM fault occurred

0 = No SRAM fault occurred

Note:

The RST condition of "P" indicates that the previous state of these bits will be preserved following a device reset using the RESET pin. Thus, pulling the RESET input low will not clear the TSD, VDUV, VDWRN, or VPUV bits.

Note:

While the VPUV bit is set, any PWONn commands will be ignored until VVPWR > 30 V.

During VPUV undervoltage condition, the Detection Event register (CLSCn, DETCn) is not cleared, unless VPWR also falls below the VPWR UVLO falling threshold (approximately18 V).

A clear on Read will not effectively clear VDUV bit as long as the VPWR undervoltage condition is maintained.

Note:

In 1-bit mode (MbitPrty = 0 in reg 0x17), the OSSE bit will be set anytime a channel within a group of 4 has OSS enabled and the OSS pin is asserted.

In 3-bit mode (MbitPrty = 1 in reg 0x17), the OSSE bit will be set anytime a 3-bit priority code is sent that is equal to or greater than the MBPn settings in registers 0x27 and 0x28 channel for a group of 4 channels.

For a 4-pair wired port, if 4P PCUT is disabled (4PPCTxx = 0 in 0x2D), the port will not be automatically turned off during a 4P-PCUT fault condition. However, the PCUTnn fault bits will still be operational, with a fault timeout equal to tOVLD. Also, if a Clear on Read is done at the Fault Event register, the PCUTnn bit is reset, and the associated summed PCUT counter is reset. Only the Channels reporting such interrupt have their counter cleared by the CoR operation. Also, clearing a PCUT fault has no impact on TLIM counter.