SLUSD53G March   2018  – August 2020 TPS23880

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Power-on Fault Register
        30. 9.6.2.30 PORT RE-MAPPING Register
        31. 9.6.2.31 Channels 1 and 2 Multi Bit Priority Register
        32. 9.6.2.32 Channels 3 and 4 Multi Bit Priority Register
        33. 9.6.2.33 4-Pair Wired and Port Power Allocation Register
        34. 9.6.2.34 4-Pair Police Ch-1 and 2 Configuration Register
        35. 9.6.2.35 4-Pair Police Ch-3 and 4 Configuration Register
        36. 9.6.2.36 TEMPERATURE Register
        37. 9.6.2.37 4-Pair Fault Configuration Register
        38. 9.6.2.38 INPUT VOLTAGE Register
        39. 9.6.2.39 CHANNEL 1 CURRENT Register
        40. 9.6.2.40 CHANNEL 2 CURRENT Register
        41. 9.6.2.41 CHANNEL 3 CURRENT Register
        42. 9.6.2.42 CHANNEL 4 CURRENT Register
        43. 9.6.2.43 CHANNEL 1 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 2 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 3 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 4 VOLTAGE Register
        47. 9.6.2.47 2x FOLDBACK SELECTION Register
        48.       95
        49. 9.6.2.48 FIRMWARE REVISION Register
        50. 9.6.2.49 I2C WATCHDOG Register
        51. 9.6.2.50 DEVICE ID Register
        52. 9.6.2.51 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.54 CHANNEL 4 DETECT RESISTANCE Register
        56. 9.6.2.55 CHANNEL 1 ASSIGNED CLASS Register
        57. 9.6.2.56 CHANNEL 2 ASSIGNED CLASS Register
        58. 9.6.2.57 CHANNEL 3 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 4 ASSIGNED CLASS Register
        60. 9.6.2.59 AUTO CLASS CONTROL Register
        61. 9.6.2.60 CHANNEL 1 AUTO CLASS POWER Register
        62. 9.6.2.61 CHANNEL 2 AUTO CLASS POWER Register
        63. 9.6.2.62 CHANNEL 3 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 4 AUTO CLASS POWER Register
        65. 9.6.2.64 ALTERNATIVE FOLDBACK Register
        66. 9.6.2.65 SRAM CONTROL Register
          1. 9.6.2.65.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.65.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.65.3 116
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.2.24 Connection Check and Auto Class Status Register

COMMAND = 1Ch with 1 Data Byte, Read Only

Figure 9-31 Connection Check and Auto Class Register Format
76543210
AC4AC3AC2AC1CC34_2CC34_1CC12_2CC12_1
R-0R-0R-0R-0R-0R-0R-0R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-34 Connection Check and Auto Class Field Descriptions
BitFieldTypeResetDescription
7–4ACnR0000bAuto Class Detection Status

1 = PD supports Auto Class

0 = PD does not support Auto Class

3–2CC34_2/1R00bConnection Check result for 4-Pair port (channels 3 and 4)
1-0CC12_2/1R00bConnection Check result for 4-Pair port (channels 1 and 2)

Auto Class:

The auto class detection measurement is completed at the end of the long classification finger, and if a PD is determined to support auto class, an auto class power measurement will be automatically completed after turn on in accordance with the IEEE auto class timing requirements.

Note:

The auto class function is operational regardless if a port is wired for 2-Pair or 4-Pair operation.

For 4-Pair single signature devices, both ACn bits will report the same result even though the classification measurement was completed on one channel.

An Auto Class power measurement will be completed shortly after power on for all channels that are found to support auto class during classification.

These measurement results are available in registers (0x51h – 0x54h), and the auto class power measurements are provide per individual channel.

Connection Check:

A connection check measurement will only be performed on 4-pair wired ports after at least one channel is found to have a valid detection result.

The results of connection check

CCnn_2CCnn_1CC Result
00"unknown" or incomplete
01Single Signature
10Dual Signature
11Reserved

These bits will be set following the completion of a connection check and prior to the setting of the Detection Event bits in the Detection Event register (0x04h).