SLVSG51A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
COMMAND = 13h with 1 Data Byte, Read/Write
Bit Descriptions: Defines the disconnect detection mechanism for each channel.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
– | – | – | – | DCDE4 | DCDE3 | DCDE2 | DCDE1 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–4 | — | R/W | 0 | |
3–0 | DCDE4–DCDE1 | R/W | 1 | DC disconnect enable
1 = DC Disconnect Enabled 0 = DC Disconnect Disabled Look at the TIMING CONFIGURATION register for more details on how to define the TDIS time period. |
DC disconnect consists in measuring the Channel DC current at SENn, starting a timer (TDIS) if this current is below a threshold and turning the Channel off if a time-out occurs. Also, the corresponding disconnect bit (DISFn) in the FAULT EVENT register is set accordingly. The TDIS counter is reset each time the current rises above the disconnect threshold for at least 3 msec. The counter does not decrement below zero.