SLUSCE3C October   2015  – August 2020 TPS2549-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FAULT Response
      2. 8.3.2  Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3  D+ and D– Protection
      4. 8.3.4  Output and D+ or D– Discharge
      5. 8.3.5  Port Power Management (PPM)
        1. 8.3.5.1 Benefits of PPM
        2. 8.3.5.2 PPM Details
        3. 8.3.5.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
        4. 8.3.5.4 Implementing PPM in a System With Two Charging Ports (DCP and DCP1)
      6. 8.3.6  CDP and SDP Auto Switch
      7. 8.3.7  Overcurrent Protection
      8. 8.3.8  Undervoltage Lockout
      9. 8.3.9  Thermal Sensing
      10. 8.3.10 Current Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 USB Specification Overview
      3. 8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
      4. 8.4.4 Charging Downstream Port (CDP) Mode
      5. 8.4.5 Dedicated Charging Port (DCP) Mode
        1. 8.4.5.1 DCP BC1.2 and YD/T 1591-2009
        2. 8.4.5.2 DCP Divider-Charging Scheme
        3. 8.4.5.3 DCP 1.2-V Charging Scheme
      6. 8.4.6 DCP Auto Mode
      7. 8.4.7 Client Mode
      8. 8.4.8 High-Bandwidth Data-Line Switches
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitance
        2. 9.2.2.2 Cable Compensation Calculation
        3. 9.2.2.3 Power Dissipation and Junction Temperature
    3. 9.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

Unless otherwise noted –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN). R(FAULT) = R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive current is into pins. Typical value is at 25°C. All voltages are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr OUT voltage rise time V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω (see Figure 7-1 and Figure 7-2) 0.7 1.14 2 ms
tf OUT voltage fall time 0.2 0.35 0.6 ms
ton OUT voltage turnon time V(IN) = 5 V, C(L) = 1 µF, R(L) = 100 Ω (see Figure 7-1 andFigure 7-4) 4.15 6 ms
toff OUT voltage turnoff time 1.8 3 ms
t(DCHG_L) Long OUT discharge hold time (SDP, CDP, or client mode to DCP_Auto) Time V(OUT) < 0.7 V (see Figure 7-3) 1.1 2 2.9 s
t(DCHG_S) Short OUT discharge hold time (DCP_Auto to SDP, CDP, or client mode) Time V(OUT) < 0.7 V (see Figure 7-3) 186 320 450 ms
t(IOS) OUT short-circuit response time(1) V(IN) = 5 V, R(SHORT) = 50 mΩ (see Figure 6-25) 2 µs
t(OC_OUT_FAULT) OUT FAULT deglitch time Bidirectional deglitch applicable to current limit condition only (no deglitch assertion for OTSD) 5.5 8 11.5 ms
tpd Analog switch propagation delay (1) V(IN) = 5 V 0.14 ns
t(SK) Analog switch skew between opposite transitions of the same port (tPHL – tPLH) (1) V(IN) = 5 V 0.02 ns
t(LD_SET) Load-detect set time V(IN) = 5 V (See Figure 6-27) 120 210 280 ms
t(LD_RESET) Load-detect reset time V(IN) = 5 V (See Figure 6-28) 1.8 3 4.2 s
t(OV_D) DP_IN and DM_IN over-voltage protection response time V(OUT) = 5 V (See Figure 6-29) 2 µs
t(OV_D_FAULT) DP_IN and DM_IN FAULT degltich time V(OUT) = 5 V (See Figure 6-30) 11 16 23 ms
(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.