SLUSCE3C October   2015  – August 2020 TPS2549-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  FAULT Response
      2. 8.3.2  Cable Compensation
        1. 8.3.2.1 Design Procedure
      3. 8.3.3  D+ and D– Protection
      4. 8.3.4  Output and D+ or D– Discharge
      5. 8.3.5  Port Power Management (PPM)
        1. 8.3.5.1 Benefits of PPM
        2. 8.3.5.2 PPM Details
        3. 8.3.5.3 Implementing PPM in a System With Two Charging Ports (CDP and SDP1)
        4. 8.3.5.4 Implementing PPM in a System With Two Charging Ports (DCP and DCP1)
      6. 8.3.6  CDP and SDP Auto Switch
      7. 8.3.7  Overcurrent Protection
      8. 8.3.8  Undervoltage Lockout
      9. 8.3.9  Thermal Sensing
      10. 8.3.10 Current Limit Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Truth Table (TT)
      2. 8.4.2 USB Specification Overview
      3. 8.4.3 Standard Downstream Port (SDP) Mode — USB 2.0 and USB 3.0
      4. 8.4.4 Charging Downstream Port (CDP) Mode
      5. 8.4.5 Dedicated Charging Port (DCP) Mode
        1. 8.4.5.1 DCP BC1.2 and YD/T 1591-2009
        2. 8.4.5.2 DCP Divider-Charging Scheme
        3. 8.4.5.3 DCP 1.2-V Charging Scheme
      6. 8.4.6 DCP Auto Mode
      7. 8.4.7 Client Mode
      8. 8.4.8 High-Bandwidth Data-Line Switches
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input and Output Capacitance
        2. 9.2.2.2 Cable Compensation Calculation
        3. 9.2.2.3 Power Dissipation and Junction Temperature
    3. 9.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Unless otherwise noted, –40°C ≤ TJ ≤ 125°C and 4.5 V ≤ V(IN) ≤ 6.5 V, V(EN) = V(IN), V(CTL1) = V(CTL2) = V(CTL3) = V(IN). R(FAULT) = R(STATUS) = 10 kΩ, R(ILIM_HI) = 19.1 kΩ, R(ILIM_LO) = 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT – POWER SWITCH
rDS(on) On-resistance(1) TJ = 25°C 47 57 mΩ
–40°C ≤ TJ ≤ 85°C 47 72
–40°C ≤TJ ≤ 125°C 47 80
Ilkg(OUT) Reverse leakage current on OUT pin VOUT = 6.5 V, VIN = VEN = 0 V, –40°C ≤ TJ ≤ 85°C, measure I(OUT) 2 µA
OUT - DISCHARGE
R(DCHG) OUT discharge resistance 400 500 630 Ω
EN, CTL1, CTL2, CTL3 INPUTS
Input pin rising logic threshold voltage 1 1.35 2 V
Input pin falling logic threshold voltage 0.85 1.15 1.65 V
Hysteresis(2) 200 mV
Input current Pin voltage = 0 V or 6.5 V –1 1 µA
CURRENT LIMIT
IOS OUT short-circuit current limit R(ILIM_LO) = 210 kΩ 205 255 305 mA
R(ILIM_LO) = 80.6 kΩ 600 660 720
R(ILIM_LO) = 23.2 kΩ 2145 2300 2455
R(ILIM_HI) = 20 kΩ 2500 2670 2840
R(ILIM_HI) = 19.1 kΩ 2620 2800 2975
R(ILIM_HI) = 15.4 kΩ 3255 3470 3685
R(ILIM_HI) = 14.7 kΩ 3411 3637 3862
R(ILIM_HI) = 12.9 kΩ 3920 4175 4435
R(ILIM_HI) = 10.4 kΩ 4830 5145 5460
R(ILIM_HI) shorted to GND 5500 7000 8000
SUPPLY CURRENT
I(IN_OFF) Disabled IN supply current V(EN) = 0 V, V(OUT) = 0 V, –40°C ≤ TJ ≤ 85°C 0.1 5 µA
I(IN_ON) Enabled IN supply current V(CTL)1 = V(CTL2) = V(CTL3) = V(IN) 220 300 µA
V(CTL1) = V(CTL2) = 0 V, V(CTL3) = V(IN) 226 300
V(CTL2) = V(IN), V(CTL1) = V(CTL3) = 0 V 150 220
V(CTL1) = V(IN), V(CTL2) = V(CTL3) = 0 V 115 190
UNDERVOLTAGE LOCKOUT, IN
V(UVLO) IN rising UVLO threshold voltage 3.9 4.1 4.3 V
Hysteresis(3) TJ = 25°C 100 mV
FAULT
Output low voltage I(FAULT) = 1 mA 100 mV
Off-state leakage V(FAULT) = 6.5 V 2 µA
STATUS
Output low voltage I(STATUS) = 1 mA 100 mV
Off-state leakage V(STATUS) = 6.5 V 2 µA
THERMAL SHUTDOWN
T(OTSD2) Thermal shutdown threshold 155 °C
T(OTSD1) Thermal shutdown threshold in current-limit 135 °C
Hysteresis(3) 20 °C
LOAD DETECT (VCTL1 = VCTL2 = VCTL3 = VIN)
I(LD) IOUT load detection threshold R(ILIM_LO) = 80.6 kΩ, rising load current 630 700 770 mA
Hysteresis(3) 50 mA
DP_IN AND DM_IN SHORT-TO-VBUS PROTECTION
V(OV) Overvoltage protection trip threshold DP_IN and DM_IN rising 3.7 3.9 4.15 V
Hysteresis(3) 100 mV
R(DCHG_Data) Discharge resistance after OVP V(DP_IN) = V(DM_IN) = 5 V 160 210 240 kΩ
CABLE COMPENSATION
I(CS) Sink current Load = 3.2 A, 2.5 V ≤ V(CS) ≤ 6.5 V 228 240 252 µA
Load = 3 A, 2.5 V ≤ V(CS) ≤ 6.5 V 214 225 236
Load = 2.4 A, 2.5 V ≤ V(CS) ≤ 6.5 V 171 180 189
Load = 2.1 A, 2.5 V ≤ V(CS) ≤ 6.5 V 149 158 166
Load = 1 A, 2.5 V ≤ V(CS) ≤ 6.5 V 70 75 80
HIGH-BANDWIDTH ANALOG SWITCH
R(HS_ON) DP and DM switch on-resistance V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30 mA 2 4 Ω
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) = –15 mA 2.9 6
|ΔR(HS_ON)| Switch resistance mismatch between DP and DM channels V(DP_OUT) = V(DM_OUT) = 0 V, I(DP_IN) = I(DM_IN) = 30 mA 0.05 0.15 Ω
V(DP_OUT) = V(DM_OUT) = 2.4 V, I(DP_IN) = I(DM_IN) = –15 mA 0.05 0.15
C(IO_OFF) DP/DM switch off-state capacitance(4) VEN = 0 V, V(DP_IN) = V(DM_IN) = 0.3 V,
Vac = 0.03 VPP , f = 1 MHz		 6.7 pF
C(IO_ON) DP/DM switch on-state capacitance(4) V(DP_IN) = V(DM_IN) = 0.3 V,
Vac = 0.03 VPP, f = 1 MHz		 10 pF
Off-state isolation(4) VEN = 0 V, f = 250 MHz 27 dB
On-state cross-channel isolation(4) f = 250 MHz 23 dB
Ilkg(OFF) Off-state leakage current, DP_OUT and DM_OUT VEN = 0 V, V(DP_IN) = V(DM_IN) = 3.6 V, V(DP_OUT) = V(DM_OUT) = 0 V 0.1 1.5 µA
BW Bandwidth (–3 dB)(4) R(L) = 50 Ω 925 MHz
CHARGING DOWNSTREAM PORT DETECT
V(DM_SRC) DM_IN CDP output voltage V(DP_IN) = 0.6 V, –250 µA < I(DM_IN) < 0 µA 0.5 0.6 0.7 V
V(DAT_REF) DP_IN rising lower window threshold for VDM_SRC activation 0.36 0.4 V
Hysteresis(4) 50 mV
V(LGC_SRC) DP_IN rising upper window threshold for VDM_SRC de-activation 0.8 0.88 V
V(LGC_SRC_HYS) Hysteresis(4) 100 mV
I(DP_SINK) DP_IN sink current V(DP_IN) = 0.6 V 40 75 100 µA
BC1.2 DCP MODE
R(DPM_SHORT) DP_IN and DM_IN shorting resistance 125 200 Ω
DIVIDER3 MODE
V(DP_DIV3) DP_IN output voltage 2.57 2.7 2.84 V
V(DM_DIV3) DM_IN output voltage 2.57 2.7 2.84 V
R(DP_DIV3) DP_IN output impedance I(DP_IN) = –5 µA 24 30 36 kΩ
R(DM_DIV3) DM_IN output impedance I(DM_IN) = –5 µA 24 30 36 kΩ
1.2-V MODE
V(DP_1.2V) DP_IN output voltage 1.12 1.2 1.26 V
V(DM_1.2V) DM_IN output voltage 1.12 1.2 1.26 V
R(DP_1.2V) DP_IN output impedance I(DP_IN) = –5 µA 84 100 126 kΩ
R(DM_1.2V) DM_IN output impedance I(DM_IN = –5 µA 84 100 126
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.
(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.
(4) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.