SLVSEG3E September   2019  – March 2022 TPS25840-Q1 , TPS25842-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO
      3. 10.3.3  Switching Frequency and Synchronization (RT/SYNC)
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 Overvoltage, IEC and Short-to-Battery Protection
        1. 10.3.11.1 V BUS and V CSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 Device Power Pins (IN, CSN/OUT, and PGND)
      17. 10.3.17 Thermal Shutdown
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
      3. 10.4.3 Device Truth Table (TT)
      4. 10.4.4 USB Port Operating Modes
        1. 10.4.4.1 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        2. 10.4.4.2 Charging Downstream Port (CDP) Mode
        3. 10.4.4.3 Client Mode
      5. 10.4.5 High-bandwidth Data-line Switches
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Support Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Limits apply over the junction temperature (TJ) range of -40°C to +150°C; VIN = 13.5 V, fSW =400 kHz, CVCC = 2.2 µF, RSNS = 15 mΩ, RIMON = 13 kΩ, RILIMIT= 13 kΩ, RSET= 300 Ω unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY VOLTATE (IN PIN)
VINOperating input voltage range4.536V
IQOperating quiescent current (non switching)VEN/UVLO = VIN, CTRL1 = CTRL2 = VCC, VCSN = 8 V, INT pull down resistance = 5.1 kΩ700990µA
ISDShutdown quiescent current; measured at IN pin.EN= 01016µA
ENABLE and UVLO (EN/UVLO PIN)
VEN/UVLO_VCC_HEN/UVLO input level required to turn on internal LDOVEN/UVLO rising threshold1.14V
VEN/UVLO_VCC_LEN/UVLO input level required to turn off internal LDOVEN/UVLO falling threshold0.3V
VEN/UVLO_HEN/UVLO input level required to turn on state machineVEN/UVLO rising threshold1.1401.2001.260V
VEN/UVLO_HYSHysteresisVEN/UVLO falling threshold90mV
ILKG_EN/UVLOEnable input leakage currentVEN/UVLO = 3.3 V0.5uA
INTERNAL LDO
VBOOT_UVLOBootstrap voltage UVLO threshold2.2V
VCCInternal LDO output voltage appearing on VCC pin6 V ≤ VIN ≤ 36 V4.7555.25V
VCC_UVLO_RRising UVLO threshold3.43.63.8V
VCC_UVLO_HYSHysteresis600mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE BUCK AVG CURRENT LIMITING
(VCSP – VCSN/OUT)Current limit voltage buck regulator control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C43.54648.5mV
(VCSP – VCSN/OUT)Current limit voltage buck regulator control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C42.54649.5mV
(VCSP – VCSN/OUT)Current limit voltage buck regulator control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 26.1 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C2022.525mV
(VCSP – VCSN/OUT)Current limit voltage buck regulator control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 26.1 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C1922.526mV
CURRENT LIMIT VOLTAGE (CSP - CSN/OUT PINS) TO ACTIVATE EXTERNAL NFET CURRENT LIMITING
(VCSP – VCSN/OUT)Current limit voltage NFET control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C404346mV
(VCSP – VCSN/OUT)Current limit voltage NFET control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 6.8 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C38.54347.5mV
(VCSP – VCSN/OUT)Current limit voltage NFET control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 125°C182124mV
(VCSP – VCSN/OUT)Current limit voltage NFET control loopVCSN = 5 V, RSET = 300 Ω, RILIMIT = 13.7 kΩ, RIMON = 13 kΩ, -40°C ≤ TJ ≤ 150°C172125mV
CURRENT LIMIT - BUCK REGULATOR PEAK CURRENT LIMIT
IL-SC-HSHigh-side current limit4.65.46.2A
IL-SC-LSLow-side current limit3.544.5A
IL-NEG-LSLow-side negative current limit–3.1–2.1–1.3A
CABLE COMPENSATION VOLTAGE
VIMONCable compensation voltage(VCSP – VCSN) = 46 mV, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ0.93511.065V
VIMONCable compensation voltage(VCSP – VCSN) = 23 mV, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = 13 kΩ0.4350.50.565V
VIMONCable compensation voltage (internal clamp)(VCSP –VCSN) = 46 mV, RSET = 300 Ω, RILIMIT = 13 kΩ, RIMON = open1.8V
BUCK OUTPUT VOLTAGE (CSN/OUT PIN)
VCSN/OUTOutput voltageINT pulldown resistance = 5.1kΩ, RIMON = 0 Ω, RILIMIT = 0 Ω5.055.105.15V
VCSN/OUTOutput voltage accuracyINT pulldown resistance = 5.1kΩ, RIMON = 0 Ω, RILIMIT = 0 Ω–11%
VCSN/OUT_OVOvervoltage level on CSN/OUT pin which buck regulator stops switchingVCSN/OUT rising7.17.57.9V
VCSN/OUT_OV_HYSHysteresis500mV
VHCCSN / OUT pin voltage required to trigger short circuit hiccup mode2V
VDROPDropout voltage ( VIN-VOUT )VIN = VOUT + VDROP, VOUT = 5.1V, IOUT = 3A150mV
BUCK REGULATOR INTERNAL RESISTANCE
RDS-ON-HSHigh-side MOSFET ON-resistanceLoad = 3 A, TJ = 25°C4045
RDS-ON-HSHigh-side MOSFET ON-resistanceLoad = 3 A, -40°C ≤ TJ ≤ 125°C4068
RDS-ON-HSHigh-side MOSFET ON-resistanceLoad = 3 A, -40°C ≤ TJ ≤ 150°C4075
RDS-ON-LSLow-side MOSFET ON-resistanceLoad = 3 A, TJ = 25C3541
RDS-ON-LSLow-side MOSFET ON-resistanceLoad = 3 A, -40°C ≤ TJ ≤ 125°C3560
RDS-ON-LSLow-side MOSFET ON-resistanceLoad = 3 A, -40°C ≤ TJ ≤ 150°C3568
NFET GATE DRIVE (LS_GD PIN)
VLS_GDNFET gate drive output voltageVCSN/OUT = 5.1 V, CG = 1000 pF (see Figure 9-2)9.51112.5V
ILS_DR_SRCNFET gate drive output source currentVCSN/OUT = 5.1 V, CG = 1000 pF234µA
ILS_DR_SNKNFET gate drive output sink currentVCSN/OUT = 5.1 V, CG = 1000 pF203550µA
VLS_GD_UVLO_RVCSN/OUT rising threshold for LS_GD operationVCSN/OUT rising2.8533.15V
VLS_GD_UVLO_HYSHysteresis80mV
BUS DISCHARGE (BUS PIN)
VBUS_OVRising threshold for BUS pin overvoltage protectionVBUS rising6.677.3V
VBUS_OV_HYSHysteresis180mV
RBUS_DCHG_18VDischarge resistance for BUSVBUS = 18V, measure leakage current29kΩ
RBUS_DCHG_8VDischarge resistance for BUSVBUS = 8V, measure leakage current35kΩ
FAULT, BUCK_ST
VOLFAULT Output low voltageISNK_PIN = 0.5 mA250mV
IOFFFAULT Off-state leakageVPIN = 5.5 V1µA
VOLBUCK_ST Output low voltageISNK_PIN = 0.5 mA250mV
IOFFBUCK_ST Off-state leakageVPIN = 5.5 V1µA
CTRL1, CTRL2 - LOGIC INPUTS
VIHRising threshold voltage1.482V
VILFalling threshold voltage0.851.30V
VHYSHysteresis180mV
IINInput current–11µA
DP_IN AND DM_IN OVERVOLTAGE PROTECTION
VDx_IN_OVRising threshold for Dx_IN overvoltage protectionDP_IN or DM_IN rising3.73.94.15V
Hysteresis100mV
RDx_IN_DCHG_18VDischarge resistance for Dx_INVDx_IN = 18V, measure leakage current94kΩ
RDx_IN_DCHG_5VDischarge resistance for Dx_INVDx_IN = 5V, measure leakage current416kΩ
HIGH-BANDWIDTH ANALOG SWITCH
RDS_ONDP and DM switch on-resistanceVDP_OUT = VDM_OUT = 0 V, IDP_IN = IDM_IN = 30 mA3.46.3Ω
RDS_ONDP and DM switch on-resistanceVDP_OUT = VDM_OUT = 2.4 V, IDP_IN = IDM_IN = –15 mA4.37.7Ω
|ΔRDS_ON|Switch resistance mismatch between DP and DM channelsVDP_OUT = VDM_OUT = 0 V, IDP_IN = IDM_IN = 30 mA0.050.15Ω
|ΔRDS_ON|Switch resistance mismatch between DP and DM channelsVDP_OUT = VDM_OUT = 2.4 V, IDP_IN = IDM_IN = –15 mA0.050.15Ω
CIO_OFFDP/DM switch off-state capacitanceVEN = 0 V, VDP_IN = VDM_IN = 0.3 V, Vac = 0.03 VPP , f = 1 MHz6.7pF
CIO_ONDP/DM switch on-state capacitanceVDP_IN = VDM_IN = 0.3 V, Vac = 0.03 VPP, f = 1 MHz10pF
OIRROff-state isolationVEN = 0 V, f = 250 MHz9dB
XTALKOn-state cross-channel isolationf = 250 MHz29dB
Ilkg(OFF)Off-state leakage current, DP_OUT and DM_OUTVEN = 0 V, VDP_IN = VDM_IN = 3.6 V, VDP_OUT = VDM_OUT = 0 V, measure IDP_OUT and IDM_OUT0.11.5µA
BWBandwidth (–3 dB)RL = 50 Ω800MHz
CHARGING DOWNSTREAM PORT (CDP) DETECT
VDM_SRCDM_IN CDP output voltageVDP_IN = 0.6 V, –250 µA < IDM_IN < 0 µA0.50.60.7V
VDAT_REFDP_IN rising lower window threshold for VDM_SRC activation0.360.380.4V
VDAT_REFHysteresis50mV
VLGC_SRCDP_IN rising upper window threshold for VDM_SRC deactivation0.80.840.88V
VLGC_SRC_HYSHysteresis100mV
IDP_SINKDP_IN sink currentVDP_IN = 0.6 V4070100µA
RT/SYNC THRESHOLD (RT/SYNC PIN)
VIH_RT/SYNCRT/SYNC high threshold for external clock synchronizationAmplitude of SYNC clock AC signal (measured at SYNC pin)3.5V
VIL_RT/SYNCRT/SYNC low threshold for external clock synchronizationAmplitude of SYNC clock AC signal (measured at SYNC pin)0.8V
THERMAL SHUTDOWN
TSDThermal shutdownShutdown threshold160°C
Recovery threshold140°C