SLVSDG2G July   2016  – December  2019 TPS2660

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Reverse Input Polarity Protection at –60-V Supply
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Reverse Input Supply Protection
      4. 9.3.4 Hot Plug-In and In-Rush Current Control
      5. 9.3.5 Overload and Short Circuit Protection
        1. 9.3.5.1 Overload Protection
          1. 9.3.5.1.1 Active Current Limiting
          2. 9.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
        2. 9.3.5.2 Short Circuit Protection
          1. 9.3.5.2.1 Start-Up With Short-Circuit On Output
        3. 9.3.5.3 FAULT Response
          1. 9.3.5.3.1 Look Ahead Overload Current Fault Indicator
        4. 9.3.5.4 Current Monitoring
        5. 9.3.5.5 IN, OUT, RTN, and GND Pins
        6. 9.3.5.6 Thermal Shutdown
        7. 9.3.5.7 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Programming the Current-Limit Threshold—R(ILIM) Selection
        3. 10.2.2.3 Undervoltage Lockout and Overvoltage Set Point
        4. 10.2.2.4 Programming Current Monitoring Resistor—RIMON
        5. 10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.5.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.5.2 Case 2: Start-Up With Load—Output Capacitance C(OUT) and Load Draws Current During Start-Up
          3. 10.2.2.5.3 Support Component Selections—RFLTb and C(IN)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Acive ORing Operation
      2. 10.3.2 Field Supply Protection in PLC, DCS I/O Modules
      3. 10.3.3 Simple 24-V Power Supply Path Protection
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHF|24
  • PWP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Undervoltage Lockout (UVLO)

Undervoltage comparator input. When the voltage at UVLO pin falls below V(UVLOF) during input power fail or input undervoltage fault, the internal FET quickly turns off and FLT is asserted. The UVLO comparator has a hysteresis of 90 mV. To set the input UVLO threshold, connect a resistor divider network from IN supply to UVLO terminal to RTN as shown in Figure 34.

TPS2660 EN_UVLO_OVP_Diagram.gifFigure 34. UVLO and OVP Thresholds Set by R1, R2 and R3

The TPS2660x also features a factory set 15-V input supply undervoltage lockout V(IN_UVLO) threshold with 1 V hysteresis. This feature can be enabled by connecting the UVLO terminal directly to the RTN terminal. If the Under-Voltage Lock-Out function is not needed, the UVLO terminal must be connected to the IN terminal. UVLO terminal must not be left floating.

The device also implements an internal power ON reset (POR) function on the IN terminal. The device disables the internal circuitry when the IN terminal voltage falls below internal POR threshold V(PORF). The internal POR threshold has a hysteresis of 275 mV.