SLVSE94F September 2018 – June 2021 TPS2663
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The TPS2663x devices incorporate circuitry to protect the system during overvoltage conditions. The TPS26630 and TPS26631 feature an accurate ± 2% adjustable overvoltage cut off functionality. A voltage more than V(OVPR) on OVP pin turns off the internal FET and protects the downstream load. To program the OVP threshold externally, connect a resistor divider from IN_SYS supply to OVP terminal to GND as shown in the Simplified Schematic.
The TPS26630 and TPS26631 also feature a factory set 34.3-V input overvoltage cut off V(IN_SYS_OVP) threshold with a 440 mV hysteresis. This feature can be enabled by connecting the OVP terminal directly to the GND terminal. The TPS26632, TPS26633 and TPS26636 feature an internally fixed 35-V maximum overvoltage clamp V(OVC) functionality. The TPS26632 and TPS26633 clamps the output voltage to V(OVC), when the input voltage exceeds 35 V. TPS26635 features a fixed 39-V maximum overvoltage clamp level. During the output voltage clamp operation, the power dissipation in the internal MOSFET is PD = (V(IN_SYS) – V(OVC)) × I(OUT). Excess power dissipation for a prolonged period can increase the device temperature. To avoid this, the internal FET is operated in overvoltage clamp for a maximum duration of tOVC(dly), 162 msec (typical). After this duration, the internal FET is turned OFF and the subsequent operation of the device depends on the MODE configuration (Auto-Retry or latch OFF) setting as shown in Table 9-1.
Figure 8-1 shows the turn ON behavior when OVP pin voltage falls below V(OVPF) threshold.
Figure 9-3 illustrates the overvoltage cut-off functionality and Figure 9-4 illustrates the overvoltage clamp functionality. FLT is asserted after a delay of 617 µs (typical) after entering in overvoltage clamp mode and remains asserted until the overvoltage fault is removed.
TPS26630 and TPS26631 | ||
TPS26635 | RLOAD = 30 Ω, FLT connected to VOUT |