SLVSE94F September   2018  – June 2021 TPS2663

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  PGOOD and PGTH
        1. 9.3.2.1 PGTH as VOUT Sensing Input
      3. 9.3.3  Undervoltage Lockout (UVLO)
      4. 9.3.4  Overvoltage Protection (OVP)
      5. 9.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 9.3.6  Reverse Current Protection
      7. 9.3.7  Overload and Short Circuit Protection
        1. 9.3.7.1 Overload Protection
          1. 9.3.7.1.1 Active Current Limiting at 1x IOL, (TPS26630 and TPS26632 Only)
          2. 9.3.7.1.2 Active Current Limiting with 2x IOL Pulse Current Support, (TPS26631, TPS26633, TPS26635 and TPS26636 Only)
        2. 9.3.7.2 Short Circuit Protection
          1. 9.3.7.2.1 Start-Up With Short-Circuit On Output
      8. 9.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only)
      9. 9.3.9  Current Monitoring Output (IMON)
      10. 9.3.10 FAULT Response ( FLT)
      11. 9.3.11 IN_SYS, IN, OUT and GND Pins
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Power Path Protection in a PLC System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Output Buffer Capacitor – COUT
        4. 10.2.2.4 PGTH Set Point
        5. 10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 10.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
      2. 10.3.2 Priority Power MUX Operation
      3. 10.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.6 Reverse Current Protection

The device monitors V(IN_SYS) and V(OUT) to provide true reverse current blocking when a reverse condition or input power failure condition is detected. The reverse comparator turns OFF the external blocking FET Q1 quickly as soon as V(IN_SYS) – V(OUT) falls below –1 V. The total time taken to turn OFF the FET Q1 in this condition is tRCB(fast_dly) + t(Driver). The delay due to the driver stage t(Driver) can be calculated using Equation 4.

Equation 4. GUID-458DC723-E6FB-4E43-B6D5-F58D513DE7E3-low.gif

where

  • RDSON(Q2) is the on resistance of the fast pull down switch Q2
  • Ciss(Q1) is the input capacitance of the blocking FET Q1
  • VGTH(Q1) is the GATE threshold voltage of the blocking FET Q1
  • VBGATE = 10.2 V (typical)

In a typical system design, t(Driver) is generally 10% to 20% of tRCB(fast_dly) of 120 nsec (typical).

Figure 9-8 and Figure 9-9 illustrates the behavior of the system during input hot short circuit condition. The blocking FET Q1 is turned ON within 1.6 ms (typical) once the differential forward voltage V(IN_SYS) – V(OUT) exceeds 67 mV (typical).

GUID-D248E5E9-8DB2-4F67-8A29-34BF3D6C7616-low.pngFigure 9-8 Input Hot Short Functionality at 24-V Supply
GUID-77EEBDF9-B8B4-480E-B7B7-AEA369D5A9B7-low.pngFigure 9-9 Input Hot-Short: Fast Trip Response (Zoomed)

The reverse comparator architecture has a supply line noise immunity resulting in a robust performance in noisy environments. This is achieved by controlling the turn OFF time of the internal FET based on the over-drive differential voltage V(IN_SYS) – V(OUT) over V(REVTH). Higher the over-drive, faster the turn OFF time, tRCB(dly).