SLVSFZ2C April   2023  – February 2024 TPS274C65

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     7
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 SPI Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Diagrams
      2. 8.3.2 SPI Mode Operation
        1. 8.3.2.1 Diagnostic Bit Behavior
      3. 8.3.3 Programmable Current Limit
        1. 8.3.3.1 Inrush Current Handling
      4. 8.3.4 DO_EN Feature
      5. 8.3.5 Protection Mechanisms
        1. 8.3.5.1 Overcurrent Protection
        2. 8.3.5.2 Short Circuit Protection
          1. 8.3.5.2.1 VS During Short-to-Ground
        3. 8.3.5.3 Inductive-Load Switching-Off Clamp
        4. 8.3.5.4 Inductive Load Demagnetization
        5. 8.3.5.5 Thermal Shutdown
        6. 8.3.5.6 Undervoltage protection on VS
        7. 8.3.5.7 Undervoltage Lockout on Low Voltage Supply (VDD_UVLO)
        8. 8.3.5.8 Power-Up and Power-Down Behavior
        9. 8.3.5.9 Reverse Current Blocking
      6. 8.3.6 Diagnostic Mechanisms
        1. 8.3.6.1 Current Sense
          1. 8.3.6.1.1 RSNS Value
            1. 8.3.6.1.1.1 SNS Output Filter
        2. 8.3.6.2 Fault Indication
          1. 8.3.6.2.1 Current Limit Behavior
        3. 8.3.6.3 Short-to-Battery and Open-Load Detection
        4. 8.3.6.4 On-State Wire-Break Detection
        5. 8.3.6.5 Off State Wire-Break Detection
        6. 8.3.6.6 ADC
      7. 8.3.7 LED Driver
    4. 8.4 Device Functional Modes
      1. 8.4.1 OFF/POR
      2. 8.4.2 INIT
      3. 8.4.3 Active
    5. 8.5 TPS274C65BS Available Registers List
    6. 8.6 TPS274C65 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IEC 61000-4-5 Surge
        2. 9.2.2.2 Loss of GND
        3. 9.2.2.3 Paralleling Channels
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 TPS274C65BS Available Registers List

The registers listed in TPS274C65 Registers section show all available registers in the AS version. Some registers are not available in the BS version. Available Registers in TPS274C65BS Version shows the registers' availability in the BS version.

Table 8-10 Available Registers in TPS274C65BS Version
ADDRESS REG_NAME FUNCTIONAL IN BS VERSION ADDRESS REG_NAME FUNCTIONAL IN BS VERSION
0x00 FAULT_TYPE_STAT Y 0x18 ADC_RESULT_CH2_V N
0x01 FAULT_CH_STAT Y 0x19 ADC_RESULT_CH3_V N
0x02 FAULT_GOBAL_TYPE Y 0x1A ADC_RESULT_CH4_V N
0x03 SHRT_VS_CH_STAT Y 0x1B ADC_RESULT_VS N
0x04 WB_OFF_CH_STAT Y 0x1C ADC_RESULT_VS_LSB N
0x05 WB_ON_CH_STAT Y 0x1D SW_STATE Y
0x06 ILIMIT_CH_STAT Y 0x1E LED_OUT_ON N
0x07 THERMAL_SD_CH_STAT Y 0x1F LED_ERR_ON N
0x08 THERMAL_WRN_CH_STAT Y 0x20 SW_FS_STATE Y
0x09 RVRS_BLK_CH_STAT N 0x21 DEV_CONFIG1 Y
0x0A RESERVED N 0x22 DEV_CONFIG2 Y
0x0B ADC_RESULT_CH1_I N 0x23 DEV_CONFIG3 See Registers with Partial BIts Available in BS
0x0C ADC_RESULT_CH1_I_LSB N 0x24 DEV_CONFIG4 Y
0x0D ADC_RESULT_CH2_I N 0x25 DEV_CONFIG5 See Registers with Partial BIts Available in BS
0x0E ADC_RESULT_CH2_I_LSB N 0x26 DEV_CONFIG6 N
0x0F ADC_RESULT_CH3_I N 0x27 FAULT_MASK See Registers with Partial BIts Available in BS
0x10 ADC_RESULT_CH3_I_LSB N 0x28 EN_WB_OFF_CH Y
0x11 ADC_RESULT_CH4_I N 0x29 EN_WB_ON_CH Y
0x12 ADC_RESULT_CH4_I_LSB N 0x2A EN_SHRT_VS_CH Y
0x13 ADC_RESULT_CH1_T N 0x2B ADC_ISNS_DIS N
0x14 ADC_RESULT_CH2_T N 0x2C ADC_TSNS_DIS N
0x15 ADC_RESULT_CH3_T N 0x2D ADC_VSNS_DIS N
0x16 ADC_RESULT_CH4_T N 0x2E ADC_CONFIG1 N
0x17 ADC_RESULT_CH1_V N 0x2F CFG_CRC Y
There are some registers contains bits that are not available in the BS version. The bits marked RSVD in Table 8-11 are not functional in the BS version.
Table 8-11 Registers with Partial Bits Available in BS
ADDRESS REG_NAME b7 b6 b5 b4 b3 b2 b1 b0
0x23 DEV_CONFIG3 RSVD ILIM_SET RSVD PARALLEL_34 PARALLEL_12 ILIM_CONFIG INRUSH_ILIM INRUSH_ILIM
0x25 DEV_CONFIG5 RSVD RSVD RSVD AUTO_RETRY_DIS WB_SVS_BLANK1 WB_SVS_BLANK0 SW_FS_CFG FLT_BIT_LTCH_DIS
0x27 FAULT_MASK MASK_SPI_ERR MASK_WD_ERR MASK_ILIMIT RSVD MASK_SHRT_VS MASK_WB_OFF MASK_WB_ON MASK_VSUV