SNVSB03D December   2018  – January 2020 TPS3840


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Circuit
      2.      TPS3840 Typical Supply Current
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. VDD Hysteresis
        2. VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. RESET Output, Active-Low
        2. RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 VDD Between VPOR and VDD(min)
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 9.2.2 Design 2: Battery Voltage and Temperature Monitor
        1. Design Requirements
        2. Detailed Design Procedure
      3. 9.2.3 Design 3: Fast Start Undervoltage Supervisor with Level-shifted Input
        1. Design Requirements
        2. Detailed Design Procedure
      4. 9.2.4 Design 4: Voltage Monitor with Back-up Battery Switchover
        1. Design Requirements
        2. Detailed Design Procedure
      5. 9.2.5 Application Curve: TPS3840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

The primary constraint for this application is monitoring a 12-V rail while preventing the VDD pin on TPS3840 from exceeding the recommended maximum of 10 V. This is accomplished by sizing the resistor divider so that when the 12-V rail drops to 10 V, the VDD pin for TPS3840 will be at 4.9 V which is the VIT- threshold for triggering a undervoltage condition for TPS3840DL49 as shown in Equation 7.

Equation 7. Vrail_trigger = VIT- x (Rtop + Rbottom) ÷ Rbottom

where Vrail_trigger is the trigger voltage of the rail being monitored, VIT- is the falling threshold on the VDD pin of TPS3840, and Rtop and Rbottom are the top and bottom resistors of the external resistor divider. Be sure to size the resistor values such that the current through the external resistor divider is much greater than IDD to preserve voltage monitoring accuracy. VIT- is fixed per device variant and is 4.9 V for TPS3840DL49. Substituting in the values from Figure 52, the undervoltage trigger threshold for the rail is set to 10.045 V.

Since the undervoltage trigger of 10 V on the rail corresponds to 4.9 V undervoltage threshold trigger of the TPS3840 device, there is plenty of room for the rail to rise up while maintaining less than 10 V on the VDD pin of the TPS3840. Equation 8 shows the maximum rail voltage that still meets the 10 V maximum at the VDD pin for TPS3840.

Equation 8. Vrail_max = 10 x (10,500 + 10,000) ÷ 10,000 = 20.5 V

This means the monitored voltage rail can go as high as 20.5 V and still not violate the recommended maximum for the VDD pin on TPS3840. This is useful when monitoring a voltage rail that has a wide range that may go much higher than the nominal rail voltage such as in this case with the specification that the 12-V rail can go as high as 18 V. Notice that the resistor values chosen are less than 100kΩ to preserve the accuracy set by the internal resistor divider. Good design practice recommends using a 0.1-µF capacitor on the VDD pin and this capacitance may need to increase when using an external resistor divider.