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Product details

Parameters

Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) Trimmable, 1.6, 1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.7, 2.8, 2.9, 3, 3.1, 3.5, 4.0, 4.2, 4.3, 4.4, 4.5, 4.6, 4.8, 4.9 Features Manual reset Reset threshold accuracy (%) 1.5 Output driver type/reset output Active-high, Active-low, Open-drain, Push-pull Time delay (ms) Programmable, 0 Rating Catalog Watchdog timer WDI (sec) None Operating temperature range (C) -40 to 125 open-in-new Find other Supervisor & reset ICs

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 open-in-new Find other Supervisor & reset ICs

Features

  • Wide operating voltage: 1.5 V to 10 V
  • Nano supply current: 300 nA (Typ), 700 nA (Max)
  • Fixed threshold voltage (VIT-)
    • Threshold from 1.6 V to 4.9 V in 0.1-V steps
    • High accuracy: 1% (Typ), 1.5% (Max)
    • Built-in hysteresis (VIT+)
      • 1.6 V < VIT- ≤ 3.0 V = 100 mV (Typical)
      • 3.1 V ≤ VIT- < 4.9 V = 200 mV (Typical)
  • Start-up delay (tSTRT): 220 µs (Typ), 350 µs (Max)
    • Programmable reset time delay (tD):
      • 50 µs (no capacitor) to 6.2 s (10-µF)
    • Active-low manual reset (MR)
    • Three output topologies:
      • TPS3840DL: open-drain, active-low (RESET), requires pull-up resistor
      • TPS3840PL: push-pull, active-low (RESET)
      • TPS3840PH: push-pull, active-high (RESET)
    • Wide temperature range: –40°C to +125°C
    • Package: SOT23-5 (DBV)

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    Description

    Wide Vin allows monitoring 9V rails or batteries without external components and 24V rails with external resistors. Nano-Iq extends battery life for low power applications and minimizes current consumption when using external resistors. Fast start-up delay allows the detection of a voltage fault before the rest of the system powers up providing maximum safety in hazardous start-up fault conditions. Low Power-on-Reset (VPOR) prevents false resets, premature enable or turn-on of next device, and proper transistor control during power-up and power-down.

    Reset output signal is asserted when the voltage at VDD drops below the negative voltage threshold (VIT-) or when manual reset (MR) is pulled to a low logic (VMR_L). Reset signal is cleared when VDD rise above VIT- plus hysteresis (VIT+) and manual reset is floating or above VMR_H and the reset time delay (tD) expires. Reset time delay can be programmed by connecting a capacitor between CT pin and ground. For a fast reset CT pin can be left floating.

    Additional features: Built-in glitch immunity protection for MR and VDD, built-in hysteresis, low open-drain output leakage current (ILKG(OD)).












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    Technical documentation

    Design & development

    For additional terms or required resources, click any title below to view the detail page where available.

    Hardware development

    EVALUATION BOARDS Download
    document-generic User guide
    $20.00
    Description

    The TPS3840 evaluation module (EVM)  is a platform for evaluating the TPS3840 device, which is a nanopower voltage supervisor with manual reset and programmable reset delay. TPS3840 offers operation up to 10 V, while maintaining very-low quiescent current of 350 nA (typ) in addition to 1 (...)

    Features
    • Manual reset
    • Programmable reset delay
    • Active-low/active-high output logic
    • Open-drain/push-pull output topology

    Design tools & simulation

    SIMULATION MODELS Download
    SNVMBN4.ZIP (2 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBN5.ZIP (51 KB) - PSpice Model
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    SNVMBN6.ZIP (51 KB) - PSpice Model
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    SNVMBN7.ZIP (2 KB) - PSpice Model
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    SNVMBN8.ZIP (2 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBN9.ZIP (52 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBR7.ZIP (97 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBR8.ZIP (98 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBR9.ZIP (97 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBS0.ZIP (98 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBS1.ZIP (98 KB) - PSpice Model
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    SNVMBS2.ZIP (106 KB) - PSpice Model
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    SNVMBS3.ZIP (107 KB) - PSpice Model
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    SNVMBS4.ZIP (98 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBS5.ZIP (98 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBS6.ZIP (98 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBS7.ZIP (97 KB) - PSpice Model
    SIMULATION MODELS Download
    SNVMBS9.ZIP (98 KB) - PSpice Model

    Reference designs

    REFERENCE DESIGNS Download
    Non-isolated power architecture with diagnostics reference design for protection relay modules
    TIDA-010055 — This reference design showcases non-isolated power supply architectures for protection relays with analog input/output and communication modules generated from 5-, 12-, or 24-V DC input. To generate the power supplies the design uses DC/DC converters with an integrated FET, a power module with an (...)
    document-generic Schematic document-generic User guide
    REFERENCE DESIGNS Download
    One-phase shunt electricity meter reference design using standalone ADCs
    TIDA-010036 — This reference design implements Class 0.5 single-phase energy measurement using standalone multi-channel analog-to-digital converters (ADC) to sample a shunt current sensor. With the combination of the shunt sensor and a compact magnetically immune power supply, the design provides protection (...)
    document-generic Schematic document-generic User guide
    REFERENCE DESIGNS Download
    Nano power, wide VIN (12 V max) supervisor reference design used as comparator or power sequencer
    TIDA-010041 — This reference design highlights a versatile use case for a low-power reset IC and a watchdog timer. With less than 1-µA current consumption, the TPS3840 device can be configured to work either as a comparator (with simple 3-pin configuration) or as a universal power supply supervisor that can (...)
    document-generic Schematic document-generic User guide
    REFERENCE DESIGNS Download
    High accuracy split-phase CT electricity meter reference design using standalone ADCs
    TIDA-010037 — This reference design implements Class 0.1 split-phase energy measurement using high-performance, multi-channel analog-to-digital converters (ADC). The independent ADC samples the output of current transformers (CT) at 8 kHz to measure the current and voltage of each leg of the AC mains. The (...)
    document-generic Schematic document-generic User guide

    CAD/CAE symbols

    Package Pins Download
    SOT-23 (DBV) 5 View options

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