SBVS300A November 2016 – September 2021 TPS3851
The watchdog is often needed to be disabled during startup to allow for an initialization period. When the initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by the TPS3851. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a TPS3890 supervisor. In this application, the TPS3890 was chosen to monitor VDD as well, which means that the RESET on the TPS3890 stays low until VDD rises above VITN. When VDD comes up, the delay time can be adjusted through the CT capacitor on the TPS3890. With this approach, the RESET delay can be adjusted from a minimum of 25 μs to a maximum of 30 seconds. For this design, a typical delay of 5 seconds is needed before the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890 data sheet) yields an ideal capacitance of 4.67 μF, giving a closest standard ceramic capacitor value of 4.7 μF. When connecting a 4.7-μF capacitor from CT to GND, the typical delay time is 5 seconds. Figure 8-5 shows that when the watchdog is disabled, the WDO output remains high. However when SET1 goes high and there is no WDI signal, WDO begins to assert. See the TPS3890 data sheet for detailed information on the TPS3890.