SLUS600E April 2004 – December 2014 TPS51100
Consider the following points before the layout of TPS51100 design begins.
As the TPS51100 is a linear regulator, the VTT current flow in both source and sink directions generates power dissipation from the device. In the source phase, the potential difference between VVLDOIN and VVTT times VTT current becomes the power dissipation, WDSRC.
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be decreased.
For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, and WDSNK, is calculated by:
Because the device does not sink and source the current at the same time and IVTT varies rapidly with time, the actual power dissipation that must be considered for thermal design is an average over the thermal relaxation duration of the system. Another power consumption is the current used for internal control circuitry from the VIN supply and VLDOIN supply. This can be estimated as 20 mW or less at normal operational conditions. This power must be effectively dissipated from the package. Maximum power dissipation allowed to the package is calculated by,
TJ(max) is 125°C
TA(max) is the maximum ambient temperature in the system
θJA is the thermal resistance from the silicon junction to the ambient
This thermal resistance strongly depends on the board layout. TPS51100 is assembled in a thermally enhanced PowerPAD package that has an exposed die pad underneath the body. For improved thermal performance, this die pad must be attached to the ground trace via thermal land on the PCB. This ground trace acts as a heat sink/spread. The typical thermal resistance, 57.7°C/W, is achieved based on a 3 mm × 2 mm thermal land with two vias without air flow. It can be improved by using larger thermal land and/or increasing the number of vias. For example, assuming a 3 mm × 3 mm thermal land with four vias without air flow, it is 45.4°C/W. Further information about the PowerPAD package and its recommended board layout is described in the PowerPAD Thermally Enhanced Package application report (SLMA002). This document is available at www.ti.com.