Product details

DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3 Control mode S3, S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.2 Vin (Max) (V) 3.6 Features S3/S5 Support Rating Catalog Operating temperature range (C) -40 to 85
DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3 Control mode S3, S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.2 Vin (Max) (V) 3.6 Features S3/S5 Support Rating Catalog Operating temperature range (C) -40 to 85
HVSSOP (DGQ) 10 9 mm² 3 x 3
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet TPS51100 3-A Sink / Source DDR Termination Regulator datasheet (Rev. E) 17 Dec 2014
Technical article 3 quiescent-current (Iq) specifications you need to understand 12 Nov 2021
Application note LDO Noise Demystified (Rev. B) 18 Aug 2020
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 09 Jul 2020
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Application note LDO PSRR Measurement Simplified (Rev. A) 09 Aug 2017
Technical article Embedded Computers with TI Power in a myriad of applications 15 May 2010
User guide Using the TPS51100 13 Jul 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS51116EVM-001 — TPS51116 Memory Power Solution, Synchronous Buck Controller Evaluation Module

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

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Simulation model

TPS51100 PSpice Model

SLVC176.ZIP (473 KB) - PSpice Model
Simulation model

TPS51100 TINA-TI Average Sink Reference Design (Rev. A)

SLVC177A.ZIP (217 KB) - TINA-TI Reference Design
Simulation model

TPS51100 TINA-TI Average Reference Design

SLVC203.ZIP (217 KB) - TINA-TI Reference Design
Simulation model

TPS51100 TINA-TI Average Spice Model

SLVC204.ZIP (7 KB) - TINA-TI Spice Model
Simulation model

TPS51100 TINA-TI Transient Spice Model

SLVC205.ZIP (7 KB) - TINA-TI Spice Model
Simulation model

TPS51100 TINA-TI Transient Reference Design

SLVC206.ZIP (216 KB) - TINA-TI Reference Design
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