Product details


DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3 Control mode S3, S5 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.5 Output VREF, VTT Vin (Min) (V) 1.2 Vin (Max) (V) 3.6 Features S3/S5 Support Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HVSSOP (DGQ) 10 9 mm² 3 x 3 open-in-new Find other DDR memory power ICs


  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications
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The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet TPS51100 3-A Sink / Source DDR Termination Regulator datasheet (Rev. E) Dec. 17, 2014
Application note LDO Noise Demystified (Rev. B) Aug. 18, 2020
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) Jul. 09, 2020
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Application note LDO PSRR Measurement Simplified (Rev. A) Aug. 09, 2017
Technical article Embedded Computers with TI Power in a myriad of applications May 15, 2010
User guide Using the TPS51100 Jul. 13, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

  • Up to 85% efficiency on the VDDQ switching regulator output
  • Dual switching regulator / LDO output for both DDR core and termination voltages
  • ± 3 A sink/source termination voltage LDO regulator
  • 10 mA termination reference voltage for DDR input reference
  • User selectable DDR and DDRII or externally referenced (...)

Design tools & simulation

SLVC176.ZIP (473 KB) - PSpice Model
SLVC177A.ZIP (217 KB) - TINA-TI Reference Design
SLVC203.ZIP (217 KB) - TINA-TI Reference Design
SLVC204.ZIP (7 KB) - TINA-TI Spice Model
SLVC205.ZIP (7 KB) - TINA-TI Spice Model
SLVC206.ZIP (216 KB) - TINA-TI Reference Design

Reference designs

Sync Buck for Intel Atom E6xx Tunnel Creek (1.8V @ 5A)
PMP5855 — The PMP5855 is designed to use a regulated 12V (8V-14V) bus to produce 10 regulated outputs in sequence for an Atom E6xx Tunnel Creek Power System. The PMP5855 is specially designed to demonstrate the TPS59610 Atom E6xx CPU and GPU Vcore regulators while providing a number of test points to evaluate (...)

CAD/CAE symbols

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Ordering & quality

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Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

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